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https://github.com/espressif/esp-idf.git
synced 2026-10-02 03:00:34 +03:00
feat(mspi): split dma and mspi alignment
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@@ -230,8 +230,6 @@ struct rmt_rx_channel_t {
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void *user_data; // user context
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rmt_rx_trans_desc_t trans_desc; // transaction description
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size_t num_dma_nodes; // number of DMA nodes, determined by how big the memory block that user configures
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size_t dma_int_mem_alignment; // DMA buffer alignment (both in size and address) for internal RX memory
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size_t dma_ext_mem_alignment; // DMA buffer alignment (both in size and address) for external RX memory
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gdma_link_list_handle_t dma_link; // DMA link list handle
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};
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@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@@ -33,6 +33,7 @@ static inline void rmt_rx_mount_dma_buffer(rmt_rx_channel_t *rx_chan, const void
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.buffer_alignment = mem_alignment,
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.flags = {
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.mark_final = GDMA_FINAL_LINK_TO_DEFAULT,
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.check_size_align = gdma_is_size_alignment_required(rx_chan->base.dma_chan),
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}
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};
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}
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@@ -53,8 +54,6 @@ static esp_err_t rmt_rx_init_dma_link(rmt_rx_channel_t *rx_channel, const rmt_rx
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.max_data_burst_size = 32,
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};
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ESP_RETURN_ON_ERROR(gdma_config_transfer(rx_channel->base.dma_chan, &transfer_cfg), TAG, "config DMA transfer failed");
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// get the alignment requirement from DMA
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gdma_get_alignment_constraints(rx_channel->base.dma_chan, &rx_channel->dma_int_mem_alignment, &rx_channel->dma_ext_mem_alignment);
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// register event callbacks
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gdma_rx_event_callbacks_t cbs = {
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@@ -63,7 +62,10 @@ static esp_err_t rmt_rx_init_dma_link(rmt_rx_channel_t *rx_channel, const rmt_rx
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// register the DMA callbacks may fail if the interrupt service can not be installed successfully
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ESP_RETURN_ON_ERROR(gdma_register_rx_event_callbacks(rx_channel->base.dma_chan, &cbs, rx_channel), TAG, "register DMA callbacks failed");
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size_t buffer_alignment = MAX(rx_channel->dma_int_mem_alignment, rx_channel->dma_ext_mem_alignment);
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// get the alignment requirement from DMA
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size_t dma_int_mem_alignment = 0, dma_ext_mem_alignment = 0;
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gdma_get_channel_alignment_constraints(rx_channel->base.dma_chan, &dma_int_mem_alignment, &dma_ext_mem_alignment, NULL);
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size_t buffer_alignment = MAX(dma_int_mem_alignment, dma_ext_mem_alignment);
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rx_channel->num_dma_nodes = esp_dma_calculate_node_count(config->mem_block_symbols * sizeof(rmt_symbol_word_t),
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buffer_alignment, DMA_DESCRIPTOR_BUFFER_MAX_SIZE);
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rx_channel->num_dma_nodes = MAX(2, rx_channel->num_dma_nodes); // at least 2 DMA nodes for ping-pong
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@@ -358,14 +360,10 @@ esp_err_t rmt_receive(rmt_channel_handle_t channel, void *buffer, size_t buffer_
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size_t mem_alignment = sizeof(rmt_symbol_word_t);
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#if SOC_RMT_SUPPORT_DMA
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uint32_t int_mem_cache_line_size = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_INT_MEM, CACHE_TYPE_DATA);
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uint32_t ext_mem_cache_line_size = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_DATA);
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if (channel->dma_chan) {
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if (esp_ptr_external_ram(buffer)) {
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mem_alignment = MAX(MAX(mem_alignment, rx_chan->dma_ext_mem_alignment), ext_mem_cache_line_size);
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} else {
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mem_alignment = MAX(MAX(mem_alignment, rx_chan->dma_int_mem_alignment), int_mem_cache_line_size);
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}
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size_t dma_alignment = gdma_get_buffer_alignment_constraint(channel->dma_chan, buffer);
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size_t cache_line_size = esp_cache_get_line_size_by_addr(buffer);
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mem_alignment = MAX(MAX(mem_alignment, dma_alignment), cache_line_size);
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}
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#endif // SOC_RMT_SUPPORT_DMA
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@@ -55,7 +55,7 @@ static esp_err_t rmt_tx_init_dma_link(rmt_tx_channel_t *tx_channel, const rmt_tx
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size_t int_alignment = 0;
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// get the alignment requirement from DMA
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gdma_get_alignment_constraints(tx_channel->base.dma_chan, &int_alignment, NULL);
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gdma_get_channel_alignment_constraints(tx_channel->base.dma_chan, &int_alignment, NULL, NULL);
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// apply RMT hardware alignment requirement
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int_alignment = MAX(int_alignment, sizeof(rmt_symbol_word_t));
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// the memory returned by `heap_caps_aligned_calloc` also meets the cache alignment requirement (both address and size)
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