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refactor(uhci): rename set_eof_mode to enable_eof_modes with bool en param

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Rename uhci_ll_rx_set_eof_mode → uhci_ll_rx_enable_eof_modes and its
parameter eof_mode → eof_modes to reflect that multiple EOF modes can
be enabled simultaneously via bitmask. Add bool en parameter so callers
can enable or disable without an outer if-check.
This commit is contained in:
morris
2026-07-24 16:21:09 +08:00
parent f7c46393b2
commit 2a9d1ee20e
12 changed files with 72 additions and 77 deletions
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components/esp_hal_uart/esp32s31/include/hal/uhci_ll.h
+8 -8
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@@ -187,21 +187,21 @@ static inline uint32_t uhci_ll_get_intr(uhci_dev_t *hw)
* @brief Set the EOF mode for payload receive
*
* @param hw Pointer to the UHCI device
* @param eof_mode The EOF mode to set. The following modes are supported:
* @param eof_modes The EOF mode to set. The following modes are supported:
* - UHCI_RX_BREAK_CHR_EOF: UHCI will end payload receive process when NULL frame is received by UART.
* - UHCI_RX_IDLE_EOF: UHCI will end payload receive process when UART has been in idle state.
* - UHCI_RX_LEN_EOF: UHCI will end payload receive process when the receiving byte count has reached the specific value.
*/
static inline void uhci_ll_rx_set_eof_mode(uhci_dev_t *hw, uint32_t eof_mode)
static inline void uhci_ll_rx_enable_eof_modes(uhci_dev_t *hw, uint32_t eof_modes, bool en)
{
if (eof_mode & UHCI_RX_BREAK_CHR_EOF) {
hw->conf0.uart_rx_brk_eof_en = 1;
if (eof_modes & UHCI_RX_BREAK_CHR_EOF) {
hw->conf0.uart_rx_brk_eof_en = en;
}
if (eof_mode & UHCI_RX_IDLE_EOF) {
hw->conf0.uart_idle_eof_en = 1;
if (eof_modes & UHCI_RX_IDLE_EOF) {
hw->conf0.uart_idle_eof_en = en;
}
if (eof_mode & UHCI_RX_LEN_EOF) {
hw->conf0.len_eof_en = 1;
if (eof_modes & UHCI_RX_LEN_EOF) {
hw->conf0.len_eof_en = en;
}
}