mirror of
https://github.com/espressif/esp-idf.git
synced 2026-10-01 18:50:34 +03:00
refactor(hal): extract assist_debug, debug_probe and trace into esp_hal_debug_assist
Move the following modules from the hal component into a new dedicated esp_hal_debug_assist component, following the esp_hal_timg pattern: - assist_debug (hal + target-specific LL headers) - debug_probe (types + target-specific LL headers) - riscv_trace (hal + types + source + target-specific LL headers) - trace_ll (esp32/esp32s2/esp32s3 target-specific LL headers) Update the following components to depend on esp_hal_debug_assist: esp_system, riscv, bootloader_support, esp_hw_support, esp_riscv_trace Remove riscv_trace_hal.c from the hal component.
This commit is contained in:
morris
@@ -1,76 +0,0 @@
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/*
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdbool.h>
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#include <stdint.h>
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#include "esp_attr.h"
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#include "soc/soc_caps.h"
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#if SOC_ASSIST_DEBUG_SUPPORTED
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#include "hal/assist_debug_ll.h"
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if SOC_ASSIST_DEBUG_SUPPORTED
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FORCE_INLINE_ATTR void assist_debug_hal_sp_int_enable(uint32_t core_id)
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{
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assist_debug_ll_sp_spill_interrupt_enable(core_id);
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}
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FORCE_INLINE_ATTR void assist_debug_hal_sp_int_disable(uint32_t core_id)
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{
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assist_debug_ll_sp_spill_interrupt_disable(core_id);
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}
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FORCE_INLINE_ATTR void assist_debug_hal_sp_int_clear(uint32_t core_id)
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{
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assist_debug_ll_sp_spill_interrupt_clear(core_id);
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}
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FORCE_INLINE_ATTR void assist_debug_hal_sp_mon_enable(uint32_t core_id)
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{
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assist_debug_ll_sp_spill_monitor_enable(core_id);
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}
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FORCE_INLINE_ATTR void assist_debug_hal_sp_mon_disable(uint32_t core_id)
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{
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assist_debug_ll_sp_spill_monitor_disable(core_id);
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}
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FORCE_INLINE_ATTR uint32_t assist_debug_hal_get_sp_ovf_pc(uint32_t core_id)
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{
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return assist_debug_ll_sp_spill_get_pc(core_id);
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}
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FORCE_INLINE_ATTR void assist_debug_hal_get_sp_bounds(uint32_t core_id, uint32_t *sp_min, uint32_t *sp_max)
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{
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if (sp_min) {
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*sp_min = assist_debug_ll_sp_spill_get_min(core_id);
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}
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if (sp_max) {
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*sp_max = assist_debug_ll_sp_spill_get_max(core_id);
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}
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}
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FORCE_INLINE_ATTR void assist_debug_hal_set_sp_bounds(uint32_t core_id, uint32_t sp_min, uint32_t sp_max)
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{
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assist_debug_ll_sp_spill_set_min(core_id, sp_min);
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assist_debug_ll_sp_spill_set_max(core_id, sp_max);
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}
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FORCE_INLINE_ATTR uint32_t assist_debug_hal_is_sp_ovf_fired(uint32_t core_id)
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{
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return assist_debug_ll_sp_spill_is_fired(core_id);
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}
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#endif // SOC_ASSIST_DEBUG_SUPPORTED
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#ifdef __cplusplus
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}
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#endif
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@@ -1,31 +0,0 @@
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/*
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* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Debug probe unit identifier (HP vs LP)
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*/
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typedef enum {
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DEBUG_PROBE_UNIT_HP = 0,
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DEBUG_PROBE_UNIT_LP = 1,
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} debug_probe_unit_id_t;
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/**
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* @brief The 32bit debug probe output can be split into two 16bit parts
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*/
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typedef enum {
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DEBUG_PROBE_SPLIT_LOWER16, ///< The lower 16 signals of the debug probe output
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DEBUG_PROBE_SPLIT_UPPER16, ///< The upper 16 signals of the debug probe output
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} debug_probe_split_u16_t;
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#ifdef __cplusplus
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}
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#endif
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@@ -1,110 +0,0 @@
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/*
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* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include <stdbool.h>
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#include "hal/riscv_trace_types.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @brief HAL context for one trace encoder core. */
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typedef struct {
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void *dev; /*!< Register block */
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int core_id; /*!< Core index */
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} riscv_trace_hal_context_t;
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/** @brief Hardware-level capture configuration. */
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typedef struct {
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uint32_t mem_start_addr; /*!< Trace memory start address */
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uint32_t mem_end_addr; /*!< Trace memory end address */
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bool mem_loop; /*!< Loop/wrap memory mode (vs stop when full) */
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bool auto_restart; /*!< Auto-restart encoder after a FIFO overflow */
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bool full_address; /*!< Full address mode (vs delta) */
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bool stall_cpu; /*!< Stall CPU when the FIFO is almost full */
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bool halt_enable; /*!< Keep tracing through hart halt */
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bool reset_enable; /*!< Keep tracing through hart reset */
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bool debug_trigger_enable; /*!< Enable Debug Module trigger input */
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uint32_t resync_mode; /*!< Resynchronization mode */
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uint32_t resync_threshold; /*!< Resynchronization counter threshold */
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uint32_t ahb_burst; /*!< AHB burst type (hburst) */
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uint32_t ahb_max_incr; /*!< Max INCR burst beats */
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uint32_t intr_mask; /*!< Interrupt enable mask (riscv_trace_intr_t flags) */
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} riscv_trace_hal_config_t;
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/** @brief One comparator of the filter unit (raw register values). */
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typedef struct {
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uint32_t input; /*!< Compared input: 0 = iaddr, 1 = tval */
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uint32_t function; /*!< Compare function: 0 ==, 1 !=, 2 <, 3 <=, 4 >, 5 >= */
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uint32_t match_value; /*!< 32-bit value compared against the input */
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bool notify; /*!< Emit a packet reporting the address that caused the match */
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} riscv_trace_hal_comparator_t;
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/** @brief Filter (trace qualifier) configuration. */
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typedef struct {
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bool enable; /*!< Master filter enable (filter_en). false = trace everything */
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bool match_comparators; /*!< Gate matching on the comparators (match_comp) */
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bool match_privilege; /*!< Gate matching on the privilege level (match_privilege) */
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bool match_ecause; /*!< Match from an exception cause (match_ecause) */
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bool match_interrupt; /*!< Match from an interrupt trap (match_interrupt) */
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bool privilege_machine; /*!< match_choice_privilege: true = machine, false = user */
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bool interrupt_itype2; /*!< match_value_interrupt: true = itype 2, false = itype 1 */
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uint32_t ecause; /*!< match_choice_ecause (6-bit exception cause code) */
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riscv_trace_hal_comparator_t primary; /*!< Primary comparator */
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riscv_trace_hal_comparator_t secondary; /*!< Secondary comparator */
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uint32_t match_mode; /*!< 0 primary only, 1 P&&S, 2 !(P&&S), 3 range (start P..until S) */
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} riscv_trace_hal_filter_config_t;
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void riscv_trace_hal_init(int core_id, const riscv_trace_hal_config_t *config, riscv_trace_hal_context_t *ctx);
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/** @brief Start tracing */
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void riscv_trace_hal_start(riscv_trace_hal_context_t *ctx);
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/** @brief Enable or disable auto-restart after FIFO overflow. */
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void riscv_trace_hal_set_auto_restart(riscv_trace_hal_context_t *ctx, bool enable);
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/** @brief Set the interrupt enable mask (see riscv_trace_intr_t flags). 0 disables all. */
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void riscv_trace_hal_set_intr_enable(riscv_trace_hal_context_t *ctx, uint32_t mask);
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/** @brief Stop tracing and wait for the FIFO to empty. */
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bool riscv_trace_hal_stop(riscv_trace_hal_context_t *ctx, uint32_t timeout_us);
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/** @brief Deinitialize the trace HAL driver */
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void riscv_trace_hal_deinit(riscv_trace_hal_context_t *ctx);
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/** @brief Read the raw TRACE_FIFO_STATUS register value. */
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uint32_t riscv_trace_hal_read_fifo_status(riscv_trace_hal_context_t *ctx);
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/** @brief Read the current (next) write address from the encoder. */
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uint32_t riscv_trace_hal_get_current_addr(riscv_trace_hal_context_t *ctx);
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/** @brief Read the raw TRACE_INTR_RAW register value. */
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uint32_t riscv_trace_hal_read_intr_raw(riscv_trace_hal_context_t *ctx);
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/** @brief Check whether TRACE_FIFO_STATUS reports an empty FIFO. */
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bool riscv_trace_hal_fifo_is_empty(uint32_t fifo_status);
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/** @brief Get the work-status field from TRACE_FIFO_STATUS. */
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riscv_trace_work_status_t riscv_trace_hal_get_work_status(uint32_t fifo_status);
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/** @brief Check whether TRACE_INTR_RAW reports trace memory full. */
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bool riscv_trace_hal_memory_is_full(uint32_t intr_status);
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/** @brief Check whether TRACE_INTR_RAW reports FIFO overflow. */
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bool riscv_trace_hal_fifo_is_overflowed(uint32_t intr_status);
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/** @brief Reset the hardware write pointer and clear interrupts before a new capture. */
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void riscv_trace_hal_prepare_capture(riscv_trace_hal_context_t *ctx);
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/** @brief Apply a filter (trace qualifier) configuration. Set before starting a capture. */
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void riscv_trace_hal_set_filter(riscv_trace_hal_context_t *ctx, const riscv_trace_hal_filter_config_t *config);
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#ifdef __cplusplus
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}
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#endif
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@@ -1,40 +0,0 @@
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/*
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* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include <stdbool.h>
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#include "esp_bit_defs.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Trace encoder interrupt flags. */
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typedef enum {
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RISCV_TRACE_INTR_FIFO_OVERFLOW = BIT(0), /*!< Trace FIFO overflowed. Some packets were lost */
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RISCV_TRACE_INTR_MEM_FULL = BIT(1), /*!< Trace memory region became full. */
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} riscv_trace_intr_t;
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/**
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* @brief Trace encoder work-status field.
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*
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* Some targets implement a narrower work_status field and only produce
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* the lower values (e.g., IDLE and WORKING). The enum is the union of
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* all observable values across targets.
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*/
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typedef enum {
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RISCV_TRACE_WORK_IDLE = 0, /*!< Encoder is not tracing */
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RISCV_TRACE_WORK_WORKING = 1, /*!< Encoder is actively tracing */
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RISCV_TRACE_WORK_WAIT = 2, /*!< Paused because the hart is halted or in reset */
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RISCV_TRACE_WORK_LOST = 3, /*!< Trace data was lost (e.g. FIFO overflow) */
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} riscv_trace_work_status_t;
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#ifdef __cplusplus
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}
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#endif
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