diff --git a/.gitlab/CODEOWNERS b/.gitlab/CODEOWNERS index 4d43f24c872..c2111013f7b 100644 --- a/.gitlab/CODEOWNERS +++ b/.gitlab/CODEOWNERS @@ -96,6 +96,7 @@ /components/esp_event/ @esp-idf-codeowners/system /components/esp_gdbstub/ @esp-idf-codeowners/debugging /components/esp_hal_*/ @esp-idf-codeowners/peripherals +/components/esp_hal_debug_assist/ @esp-idf-codeowners/peripherals @esp-idf-codeowners/debugging /components/esp_hal_ieee802154/ @esp-idf-codeowners/ieee802154 /components/esp_hal_pmu/ @esp-idf-codeowners/power-management @esp-idf-codeowners/peripherals /components/esp_hal_rtc_timer/ @esp-idf-codeowners/power-management @esp-idf-codeowners/peripherals diff --git a/components/bootloader_support/CMakeLists.txt b/components/bootloader_support/CMakeLists.txt index 98bae2bae7e..3338b065aed 100644 --- a/components/bootloader_support/CMakeLists.txt +++ b/components/bootloader_support/CMakeLists.txt @@ -82,7 +82,7 @@ if(BOOTLOADER_BUILD OR CONFIG_APP_BUILD_TYPE_RAM) endif() # `esp_hal_ana_conv` is required by bootloader_random_esp32xx.c list(APPEND priv_requires esp_hal_wdt esp_hal_gpio esp_hal_uart esp_hal_ana_conv esp_hal_rtc_timer - esp_hal_clock esp_hal_security) + esp_hal_clock esp_hal_security esp_hal_debug_assist) list(APPEND srcs "src/bootloader_reset_common.c" "src/bootloader_init.c" @@ -102,7 +102,7 @@ else() set(priv_requires spi_flash mbedtls efuse heap esp_bootloader_format esp_app_format esptool_py) # `esp_hal_ana_conv` is required by bootloader_random_esp32xx.c list(APPEND priv_requires esp_hal_wdt esp_hal_gpio esp_hal_uart esp_hal_ana_conv esp_hal_rtc_timer - esp_hal_clock esp_hal_security) + esp_hal_clock esp_hal_security esp_hal_debug_assist) endif() # src/flash_encrypt.c includes esp_security/esp_key_mgr.h on diff --git a/components/esp_hal_debug_assist/CMakeLists.txt b/components/esp_hal_debug_assist/CMakeLists.txt new file mode 100644 index 00000000000..9680e80a4a7 --- /dev/null +++ b/components/esp_hal_debug_assist/CMakeLists.txt @@ -0,0 +1,16 @@ +idf_build_get_property(target IDF_TARGET) +if(${target} STREQUAL "linux") + return() # This component is not supported by the POSIX/Linux simulator +endif() + +set(srcs) +set(public_include "include" "${target}/include") + +if(CONFIG_SOC_RISCV_TRACE_SUPPORTED) + list(APPEND srcs "riscv_trace_hal.c") +endif() + +idf_component_register(SRCS ${srcs} + INCLUDE_DIRS ${public_include} + REQUIRES soc hal + PRIV_REQUIRES esp_rom) diff --git a/components/esp_hal_debug_assist/README.md b/components/esp_hal_debug_assist/README.md new file mode 100644 index 00000000000..c80e2dd97ba --- /dev/null +++ b/components/esp_hal_debug_assist/README.md @@ -0,0 +1,66 @@ +# ESP Hardware Abstraction Layer for Debug Assist Peripherals + +> [!NOTE] +> This component is currently in beta. Its API, behavior, and compatibility may change at any time and without notice; backward compatibility is not guaranteed. Use caution when integrating into production systems. + +## Overview + +The `esp_hal_debug_assist` component provides a **Hardware Abstraction Layer** for various debug and hardware-assisted monitoring peripherals found across ESP targets. It collects low-level register access code and HAL-level sequencing into a single reusable component, making it straightforward for bare-metal users and porting efforts to leverage these debugging features without depending on the full ESP-IDF driver stack. + +## Submodules + +### 1. assist_debug — Stack Spill & Bus Monitor + +The assist_debug (a.k.a. bus monitor) peripheral monitors CPU stack pointer usage and reports stack overflow/underflow conditions. + +Key capabilities: + +- SP upper/lower bound monitoring with interrupt on overflow +- PC recording on SP overflow (supported targets) +- Debug module active detection (`assist_debug_ll_is_debugger_active`) +- CPU lockup capture with exception cause, tval, and iaddr trace +- Lockup-triggered hardware reset via LP_CLKRST + +### 2. debug_probe — Signal Probing (Logic Analyzer) + +The debug probe peripheral routes internal digital signals to GPIO pads for real-time observation with a logic analyzer or oscilloscope. + +Key capabilities: + +- Two independent probe units: HP (high-performance) and LP (low-power) +- Two channels per unit, each routing 32 bits of internal signals +- Configurable signal group selection per byte lane +- 16-bit or 32-bit output to GPIO pads + +### 3. riscv_trace — RISC-V Trace Encoder + +The RISC-V trace encoder captures instruction trace packets to a reserved memory region. + +Key capabilities: + +- Programmable memory region (start/end address, wrap or stop modes) +- Configurable trace options: full/delta address, stall-on-full, halt/reset behavior +- Filter unit with dual comparators (address/value match, range, privilege level filtering) +- Interrupt on FIFO overflow or memory-full condition +- Configurable AHB burst and resynchronization parameters + +### 4. xtensa_trace_ll — Xtensa Trace Memory Management + +Low-level helpers for Xtensa trace memory management. + +## Architecture + +Each submodule follows the same two-layer design: + +1. **HAL Layer** (`include/hal/*_hal.h`, `*_hal.c`): Defines initialization sequences, configuration structures, and operational flow. Not all submodules have a .c file — simple ones are entirely inline. + +2. **Low-Level Layer** (`/include/hal/*_ll.h`): Chip-specific register access. One implementation per target that has the peripheral. + +File inclusion follows the pattern `/include/hal/` — the build system automatically picks the right LL header for the selected target. + +## Dependencies + +- `soc`: Chip-specific register definitions and structs +- `hal`: Core hardware abstraction utilities (`hal/assert.h`, `hal/misc.h`) +- `esp_common`: Attribute macros and bit definitions (`esp_attr.h`, `esp_bit_defs.h`) +- `esp_rom` (priv): ROM delay functions used by `riscv_trace_hal.c` diff --git a/components/hal/esp32/include/hal/trace_ll.h b/components/esp_hal_debug_assist/esp32/include/hal/xtensa_trace_ll.h similarity index 89% rename from components/hal/esp32/include/hal/trace_ll.h rename to components/esp_hal_debug_assist/esp32/include/hal/xtensa_trace_ll.h index a81fd83dace..e6f25c22d4d 100644 --- a/components/hal/esp32/include/hal/trace_ll.h +++ b/components/esp_hal_debug_assist/esp32/include/hal/xtensa_trace_ll.h @@ -13,12 +13,14 @@ extern "C" { #endif +__attribute__((always_inline)) static inline void trace_ll_mem_enable(int cpu, bool enable) { int reg[] = {DPORT_PRO_TRACEMEM_ENA_REG, DPORT_APP_TRACEMEM_ENA_REG}; DPORT_WRITE_PERI_REG(reg[cpu], enable); } +__attribute__((always_inline)) static inline void trace_ll_set_mode(int mode) { DPORT_WRITE_PERI_REG(DPORT_TRACEMEM_MUX_MODE_REG, mode); diff --git a/components/hal/esp32c2/include/hal/assist_debug_ll.h b/components/esp_hal_debug_assist/esp32c2/include/hal/assist_debug_ll.h similarity index 66% rename from components/hal/esp32c2/include/hal/assist_debug_ll.h rename to components/esp_hal_debug_assist/esp32c2/include/hal/assist_debug_ll.h index 6e943c8f239..f6b4da484c3 100644 --- a/components/hal/esp32c2/include/hal/assist_debug_ll.h +++ b/components/esp_hal_debug_assist/esp32c2/include/hal/assist_debug_ll.h @@ -4,11 +4,10 @@ * SPDX-License-Identifier: Apache-2.0 */ -// The LL layer for DEBUG_ASSIST peripheral - #pragma once #include "soc/assist_debug_reg.h" + #define ASSIST_DEBUG_SP_SPILL_BITS (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA | ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA) #define ASSIST_DEBUG_CORE_0_MONITOR_REG ASSIST_DEBUG_CORE_0_INTR_ENA_REG @@ -16,7 +15,6 @@ #include #include -#include "esp_attr.h" #include "hal/assert.h" #include "soc/system_struct.h" @@ -59,77 +57,92 @@ extern "C" { /* These functions are optimized and designed for internal usage. * So, the API may differ from general ll layer pattern */ -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_monitor_enable(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_monitor_enable(__attribute__((unused)) uint32_t core_id) { REG_SET_BIT(ASSIST_DEBUG_CORE_0_INTR_ENA_REG, ASSIST_DEBUG_SP_SPILL_BITS); } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_monitor_disable(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_monitor_disable(__attribute__((unused)) uint32_t core_id) { REG_CLR_BIT(ASSIST_DEBUG_CORE_0_INTR_ENA_REG, ASSIST_DEBUG_SP_SPILL_BITS); } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_interrupt_enable(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_interrupt_enable(__attribute__((unused)) uint32_t core_id) { REG_SET_BIT(ASSIST_DEBUG_CORE_0_INTR_RLS_REG, ASSIST_DEBUG_SP_SPILL_BITS); } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_interrupt_disable(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_interrupt_disable(__attribute__((unused)) uint32_t core_id) { REG_CLR_BIT(ASSIST_DEBUG_CORE_0_INTR_RLS_REG, ASSIST_DEBUG_SP_SPILL_BITS); } -FORCE_INLINE_ATTR bool assist_debug_ll_sp_spill_is_fired(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline bool assist_debug_ll_sp_spill_is_fired(__attribute__((unused)) uint32_t core_id) { return REG_READ(ASSIST_DEBUG_CORE_0_INTR_RAW_REG) & ASSIST_DEBUG_SP_SPILL_BITS; } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_interrupt_clear(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_interrupt_clear(__attribute__((unused)) uint32_t core_id) { REG_WRITE(ASSIST_DEBUG_CORE_0_INTR_CLR_REG, ASSIST_DEBUG_SP_SPILL_BITS); } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_set_min(__attribute__((unused)) uint32_t core_id, uint32_t min) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_set_min(__attribute__((unused)) uint32_t core_id, uint32_t min) { REG_WRITE(ASSIST_DEBUG_CORE_0_SP_MIN_REG, min); } -FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_min(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline uint32_t assist_debug_ll_sp_spill_get_min(__attribute__((unused)) uint32_t core_id) { return REG_READ(ASSIST_DEBUG_CORE_0_SP_MIN_REG); } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_set_max(__attribute__((unused)) uint32_t core_id, uint32_t max) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_set_max(__attribute__((unused)) uint32_t core_id, uint32_t max) { REG_WRITE(ASSIST_DEBUG_CORE_0_SP_MAX_REG, max); } -FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_max(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline uint32_t assist_debug_ll_sp_spill_get_max(__attribute__((unused)) uint32_t core_id) { return REG_READ(ASSIST_DEBUG_CORE_0_SP_MAX_REG); } -FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_pc(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline uint32_t assist_debug_ll_sp_spill_get_pc(__attribute__((unused)) uint32_t core_id) { return REG_READ(ASSIST_DEBUG_CORE_0_SP_PC_REG); } -FORCE_INLINE_ATTR void assist_debug_ll_enable_pc_recording(uint32_t core_id, bool enable) +__attribute__((always_inline)) +static inline void assist_debug_ll_enable_pc_recording(uint32_t core_id, bool enable) { } -FORCE_INLINE_ATTR void assist_debug_ll_enable_bus_clock(__attribute__((unused)) uint32_t core_id, bool enable) +__attribute__((always_inline)) +static inline void assist_debug_ll_enable_bus_clock(__attribute__((unused)) uint32_t core_id, bool enable) { SYSTEM.cpu_peri_clk_en.clk_en_assist_debug = enable; } -FORCE_INLINE_ATTR void assist_debug_ll_reset_register(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_reset_register(__attribute__((unused)) uint32_t core_id) { SYSTEM.cpu_peri_rst_en.rst_en_assist_debug = true; SYSTEM.cpu_peri_rst_en.rst_en_assist_debug = false; } -FORCE_INLINE_ATTR bool assist_debug_ll_is_debugger_active(void) +__attribute__((always_inline)) +static inline bool assist_debug_ll_is_debugger_active(void) { return REG_GET_BIT(ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG, ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE); } diff --git a/components/hal/esp32c3/include/hal/assist_debug_ll.h b/components/esp_hal_debug_assist/esp32c3/include/hal/assist_debug_ll.h similarity index 66% rename from components/hal/esp32c3/include/hal/assist_debug_ll.h rename to components/esp_hal_debug_assist/esp32c3/include/hal/assist_debug_ll.h index b5a5043c5dd..5ef55debceb 100644 --- a/components/hal/esp32c3/include/hal/assist_debug_ll.h +++ b/components/esp_hal_debug_assist/esp32c3/include/hal/assist_debug_ll.h @@ -4,11 +4,10 @@ * SPDX-License-Identifier: Apache-2.0 */ -// The LL layer for DEBUG_ASSIST peripheral - #pragma once #include "soc/assist_debug_reg.h" + #define ASSIST_DEBUG_SP_SPILL_BITS (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA | ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA) #define ASSIST_DEBUG_CORE_0_MONITOR_REG ASSIST_DEBUG_CORE_0_INTR_ENA_REG @@ -16,7 +15,6 @@ #include #include -#include "esp_attr.h" #include "hal/assert.h" #include "soc/system_struct.h" @@ -59,77 +57,92 @@ extern "C" { /* These functions are optimized and designed for internal usage. * So, the API may differ from general ll layer pattern */ -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_monitor_enable(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_monitor_enable(__attribute__((unused)) uint32_t core_id) { REG_SET_BIT(ASSIST_DEBUG_CORE_0_INTR_ENA_REG, ASSIST_DEBUG_SP_SPILL_BITS); } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_monitor_disable(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_monitor_disable(__attribute__((unused)) uint32_t core_id) { REG_CLR_BIT(ASSIST_DEBUG_CORE_0_INTR_ENA_REG, ASSIST_DEBUG_SP_SPILL_BITS); } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_interrupt_enable(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_interrupt_enable(__attribute__((unused)) uint32_t core_id) { REG_SET_BIT(ASSIST_DEBUG_CORE_0_INTR_RLS_REG, ASSIST_DEBUG_SP_SPILL_BITS); } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_interrupt_disable(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_interrupt_disable(__attribute__((unused)) uint32_t core_id) { REG_CLR_BIT(ASSIST_DEBUG_CORE_0_INTR_RLS_REG, ASSIST_DEBUG_SP_SPILL_BITS); } -FORCE_INLINE_ATTR bool assist_debug_ll_sp_spill_is_fired(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline bool assist_debug_ll_sp_spill_is_fired(__attribute__((unused)) uint32_t core_id) { return REG_READ(ASSIST_DEBUG_CORE_0_INTR_RAW_REG) & ASSIST_DEBUG_SP_SPILL_BITS; } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_interrupt_clear(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_interrupt_clear(__attribute__((unused)) uint32_t core_id) { REG_WRITE(ASSIST_DEBUG_CORE_0_INTR_CLR_REG, ASSIST_DEBUG_SP_SPILL_BITS); } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_set_min(__attribute__((unused)) uint32_t core_id, uint32_t min) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_set_min(__attribute__((unused)) uint32_t core_id, uint32_t min) { REG_WRITE(ASSIST_DEBUG_CORE_0_SP_MIN_REG, min); } -FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_min(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline uint32_t assist_debug_ll_sp_spill_get_min(__attribute__((unused)) uint32_t core_id) { return REG_READ(ASSIST_DEBUG_CORE_0_SP_MIN_REG); } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_set_max(__attribute__((unused)) uint32_t core_id, uint32_t max) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_set_max(__attribute__((unused)) uint32_t core_id, uint32_t max) { REG_WRITE(ASSIST_DEBUG_CORE_0_SP_MAX_REG, max); } -FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_max(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline uint32_t assist_debug_ll_sp_spill_get_max(__attribute__((unused)) uint32_t core_id) { return REG_READ(ASSIST_DEBUG_CORE_0_SP_MAX_REG); } -FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_pc(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline uint32_t assist_debug_ll_sp_spill_get_pc(__attribute__((unused)) uint32_t core_id) { return REG_READ(ASSIST_DEBUG_CORE_0_SP_PC_REG); } -FORCE_INLINE_ATTR void assist_debug_ll_enable_pc_recording(uint32_t core_id, bool enable) +__attribute__((always_inline)) +static inline void assist_debug_ll_enable_pc_recording(uint32_t core_id, bool enable) { } -FORCE_INLINE_ATTR void assist_debug_ll_enable_bus_clock(__attribute__((unused)) uint32_t core_id, bool enable) +__attribute__((always_inline)) +static inline void assist_debug_ll_enable_bus_clock(__attribute__((unused)) uint32_t core_id, bool enable) { SYSTEM.cpu_peri_clk_en.reg_clk_en_assist_debug = enable; } -FORCE_INLINE_ATTR void assist_debug_ll_reset_register(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_reset_register(__attribute__((unused)) uint32_t core_id) { SYSTEM.cpu_peri_rst_en.reg_rst_en_assist_debug = true; SYSTEM.cpu_peri_rst_en.reg_rst_en_assist_debug = false; } -FORCE_INLINE_ATTR bool assist_debug_ll_is_debugger_active(void) +__attribute__((always_inline)) +static inline bool assist_debug_ll_is_debugger_active(void) { return REG_GET_BIT(ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG, ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE); } diff --git a/components/hal/esp32c5/include/hal/assist_debug_ll.h b/components/esp_hal_debug_assist/esp32c5/include/hal/assist_debug_ll.h similarity index 66% rename from components/hal/esp32c5/include/hal/assist_debug_ll.h rename to components/esp_hal_debug_assist/esp32c5/include/hal/assist_debug_ll.h index d4eda57f483..dffbf09b4f2 100644 --- a/components/hal/esp32c5/include/hal/assist_debug_ll.h +++ b/components/esp_hal_debug_assist/esp32c5/include/hal/assist_debug_ll.h @@ -4,11 +4,10 @@ * SPDX-License-Identifier: Apache-2.0 */ -// The LL layer for DEBUG_ASSIST peripheral - #pragma once #include "soc/assist_debug_reg.h" + #define BUS_MONITOR_SP_SPILL_BITS (BUS_MONITOR_CORE_0_SP_SPILL_MIN_ENA | BUS_MONITOR_CORE_0_SP_SPILL_MAX_ENA) #define BUS_MONITOR_CORE_0_MONITOR_REG BUS_MONITOR_CORE_0_MONTR_ENA_REG // Compatible alias @@ -19,7 +18,6 @@ #include #include -#include "esp_attr.h" #include "hal/assert.h" #include "soc/pcr_struct.h" @@ -61,77 +59,92 @@ extern "C" { /* These functions are optimized and designed for internal usage. * So, the API may differ from general ll layer pattern */ -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_monitor_enable(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_monitor_enable(__attribute__((unused)) uint32_t core_id) { REG_SET_BIT(BUS_MONITOR_CORE_0_MONTR_ENA_REG, BUS_MONITOR_SP_SPILL_BITS); } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_monitor_disable(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_monitor_disable(__attribute__((unused)) uint32_t core_id) { REG_CLR_BIT(BUS_MONITOR_CORE_0_MONTR_ENA_REG, BUS_MONITOR_SP_SPILL_BITS); } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_interrupt_enable(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_interrupt_enable(__attribute__((unused)) uint32_t core_id) { REG_SET_BIT(BUS_MONITOR_CORE_0_INTR_ENA_REG, BUS_MONITOR_SP_SPILL_BITS); } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_interrupt_disable(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_interrupt_disable(__attribute__((unused)) uint32_t core_id) { REG_CLR_BIT(BUS_MONITOR_CORE_0_INTR_ENA_REG, BUS_MONITOR_SP_SPILL_BITS); } -FORCE_INLINE_ATTR bool assist_debug_ll_sp_spill_is_fired(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline bool assist_debug_ll_sp_spill_is_fired(__attribute__((unused)) uint32_t core_id) { return REG_READ(BUS_MONITOR_CORE_0_INTR_RAW_REG) & BUS_MONITOR_SP_SPILL_BITS; } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_interrupt_clear(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_interrupt_clear(__attribute__((unused)) uint32_t core_id) { REG_WRITE(BUS_MONITOR_CORE_0_INTR_CLR_REG, BUS_MONITOR_SP_SPILL_BITS); } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_set_min(__attribute__((unused)) uint32_t core_id, uint32_t min) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_set_min(__attribute__((unused)) uint32_t core_id, uint32_t min) { REG_WRITE(BUS_MONITOR_CORE_0_SP_MIN_REG, min); } -FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_min(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline uint32_t assist_debug_ll_sp_spill_get_min(__attribute__((unused)) uint32_t core_id) { return REG_READ(BUS_MONITOR_CORE_0_SP_MIN_REG); } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_set_max(__attribute__((unused)) uint32_t core_id, uint32_t max) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_set_max(__attribute__((unused)) uint32_t core_id, uint32_t max) { REG_WRITE(BUS_MONITOR_CORE_0_SP_MAX_REG, max); } -FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_max(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline uint32_t assist_debug_ll_sp_spill_get_max(__attribute__((unused)) uint32_t core_id) { return REG_READ(BUS_MONITOR_CORE_0_SP_MAX_REG); } -FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_pc(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline uint32_t assist_debug_ll_sp_spill_get_pc(__attribute__((unused)) uint32_t core_id) { return REG_READ(BUS_MONITOR_CORE_0_SP_PC_REG); } -FORCE_INLINE_ATTR void assist_debug_ll_enable_pc_recording(uint32_t core_id, bool enable) +__attribute__((always_inline)) +static inline void assist_debug_ll_enable_pc_recording(uint32_t core_id, bool enable) { } -FORCE_INLINE_ATTR void assist_debug_ll_enable_bus_clock(__attribute__((unused)) uint32_t core_id, bool enable) +__attribute__((always_inline)) +static inline void assist_debug_ll_enable_bus_clock(__attribute__((unused)) uint32_t core_id, bool enable) { PCR.assist_conf.assist_clk_en = enable; } -FORCE_INLINE_ATTR void assist_debug_ll_reset_register(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_reset_register(__attribute__((unused)) uint32_t core_id) { PCR.assist_conf.assist_rst_en = true; PCR.assist_conf.assist_rst_en = false; } -FORCE_INLINE_ATTR bool assist_debug_ll_is_debugger_active(void) +__attribute__((always_inline)) +static inline bool assist_debug_ll_is_debugger_active(void) { return REG_GET_BIT(ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG, ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE); } diff --git a/components/hal/esp32c6/include/hal/assist_debug_ll.h b/components/esp_hal_debug_assist/esp32c6/include/hal/assist_debug_ll.h similarity index 66% rename from components/hal/esp32c6/include/hal/assist_debug_ll.h rename to components/esp_hal_debug_assist/esp32c6/include/hal/assist_debug_ll.h index 9c559815cc4..1231172b3ef 100644 --- a/components/hal/esp32c6/include/hal/assist_debug_ll.h +++ b/components/esp_hal_debug_assist/esp32c6/include/hal/assist_debug_ll.h @@ -4,11 +4,10 @@ * SPDX-License-Identifier: Apache-2.0 */ -// The LL layer for DEBUG_ASSIST peripheral - #pragma once #include "soc/assist_debug_reg.h" + #define ASSIST_DEBUG_SP_SPILL_BITS (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA | ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA) #define ASSIST_DEBUG_CORE_0_MONITOR_REG ASSIST_DEBUG_CORE_0_INTR_ENA_REG @@ -16,7 +15,6 @@ #include #include -#include "esp_attr.h" #include "hal/assert.h" #include "soc/pcr_struct.h" @@ -59,77 +57,92 @@ extern "C" { /* These functions are optimized and designed for internal usage. * So, the API may differ from general ll layer pattern */ -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_monitor_enable(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_monitor_enable(__attribute__((unused)) uint32_t core_id) { REG_SET_BIT(ASSIST_DEBUG_CORE_0_INTR_ENA_REG, ASSIST_DEBUG_SP_SPILL_BITS); } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_monitor_disable(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_monitor_disable(__attribute__((unused)) uint32_t core_id) { REG_CLR_BIT(ASSIST_DEBUG_CORE_0_INTR_ENA_REG, ASSIST_DEBUG_SP_SPILL_BITS); } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_interrupt_enable(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_interrupt_enable(__attribute__((unused)) uint32_t core_id) { REG_SET_BIT(ASSIST_DEBUG_CORE_0_INTR_RLS_REG, ASSIST_DEBUG_SP_SPILL_BITS); } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_interrupt_disable(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_interrupt_disable(__attribute__((unused)) uint32_t core_id) { REG_CLR_BIT(ASSIST_DEBUG_CORE_0_INTR_RLS_REG, ASSIST_DEBUG_SP_SPILL_BITS); } -FORCE_INLINE_ATTR bool assist_debug_ll_sp_spill_is_fired(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline bool assist_debug_ll_sp_spill_is_fired(__attribute__((unused)) uint32_t core_id) { return REG_READ(ASSIST_DEBUG_CORE_0_INTR_RAW_REG) & ASSIST_DEBUG_SP_SPILL_BITS; } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_interrupt_clear(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_interrupt_clear(__attribute__((unused)) uint32_t core_id) { REG_WRITE(ASSIST_DEBUG_CORE_0_INTR_CLR_REG, ASSIST_DEBUG_SP_SPILL_BITS); } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_set_min(__attribute__((unused)) uint32_t core_id, uint32_t min) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_set_min(__attribute__((unused)) uint32_t core_id, uint32_t min) { REG_WRITE(ASSIST_DEBUG_CORE_0_SP_MIN_REG, min); } -FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_min(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline uint32_t assist_debug_ll_sp_spill_get_min(__attribute__((unused)) uint32_t core_id) { return REG_READ(ASSIST_DEBUG_CORE_0_SP_MIN_REG); } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_set_max(__attribute__((unused)) uint32_t core_id, uint32_t max) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_set_max(__attribute__((unused)) uint32_t core_id, uint32_t max) { REG_WRITE(ASSIST_DEBUG_CORE_0_SP_MAX_REG, max); } -FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_max(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline uint32_t assist_debug_ll_sp_spill_get_max(__attribute__((unused)) uint32_t core_id) { return REG_READ(ASSIST_DEBUG_CORE_0_SP_MAX_REG); } -FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_pc(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline uint32_t assist_debug_ll_sp_spill_get_pc(__attribute__((unused)) uint32_t core_id) { return REG_READ(ASSIST_DEBUG_CORE_0_SP_PC_REG); } -FORCE_INLINE_ATTR void assist_debug_ll_enable_pc_recording(uint32_t core_id, bool enable) +__attribute__((always_inline)) +static inline void assist_debug_ll_enable_pc_recording(uint32_t core_id, bool enable) { } -FORCE_INLINE_ATTR void assist_debug_ll_enable_bus_clock(__attribute__((unused)) uint32_t core_id, bool enable) +__attribute__((always_inline)) +static inline void assist_debug_ll_enable_bus_clock(__attribute__((unused)) uint32_t core_id, bool enable) { PCR.assist_conf.assist_clk_en = enable; } -FORCE_INLINE_ATTR void assist_debug_ll_reset_register(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_reset_register(__attribute__((unused)) uint32_t core_id) { PCR.assist_conf.assist_rst_en = true; PCR.assist_conf.assist_rst_en = false; } -FORCE_INLINE_ATTR bool assist_debug_ll_is_debugger_active(void) +__attribute__((always_inline)) +static inline bool assist_debug_ll_is_debugger_active(void) { return REG_GET_BIT(ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG, ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE); } diff --git a/components/hal/esp32c61/include/hal/assist_debug_ll.h b/components/esp_hal_debug_assist/esp32c61/include/hal/assist_debug_ll.h similarity index 66% rename from components/hal/esp32c61/include/hal/assist_debug_ll.h rename to components/esp_hal_debug_assist/esp32c61/include/hal/assist_debug_ll.h index 505fd716175..b5a488748d8 100644 --- a/components/hal/esp32c61/include/hal/assist_debug_ll.h +++ b/components/esp_hal_debug_assist/esp32c61/include/hal/assist_debug_ll.h @@ -4,11 +4,10 @@ * SPDX-License-Identifier: Apache-2.0 */ -// The LL layer for DEBUG_ASSIST peripheral - #pragma once #include "soc/assist_debug_reg.h" + #define BUS_MONITOR_SP_SPILL_BITS (BUS_MONITOR_CORE_0_SP_SPILL_MIN_ENA | BUS_MONITOR_CORE_0_SP_SPILL_MAX_ENA) #define BUS_MONITOR_CORE_0_MONITOR_REG BUS_MONITOR_CORE_0_MONTR_ENA_REG // Compatible alias @@ -19,7 +18,6 @@ #include #include -#include "esp_attr.h" #include "hal/assert.h" #include "soc/pcr_struct.h" @@ -61,77 +59,92 @@ extern "C" { /* These functions are optimized and designed for internal usage. * So, the API may differ from general ll layer pattern */ -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_monitor_enable(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_monitor_enable(__attribute__((unused)) uint32_t core_id) { REG_SET_BIT(BUS_MONITOR_CORE_0_MONTR_ENA_REG, BUS_MONITOR_SP_SPILL_BITS); } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_monitor_disable(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_monitor_disable(__attribute__((unused)) uint32_t core_id) { REG_CLR_BIT(BUS_MONITOR_CORE_0_MONTR_ENA_REG, BUS_MONITOR_SP_SPILL_BITS); } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_interrupt_enable(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_interrupt_enable(__attribute__((unused)) uint32_t core_id) { REG_SET_BIT(BUS_MONITOR_CORE_0_INTR_ENA_REG, BUS_MONITOR_SP_SPILL_BITS); } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_interrupt_disable(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_interrupt_disable(__attribute__((unused)) uint32_t core_id) { REG_CLR_BIT(BUS_MONITOR_CORE_0_INTR_ENA_REG, BUS_MONITOR_SP_SPILL_BITS); } -FORCE_INLINE_ATTR bool assist_debug_ll_sp_spill_is_fired(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline bool assist_debug_ll_sp_spill_is_fired(__attribute__((unused)) uint32_t core_id) { return REG_READ(BUS_MONITOR_CORE_0_INTR_RAW_REG) & BUS_MONITOR_SP_SPILL_BITS; } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_interrupt_clear(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_interrupt_clear(__attribute__((unused)) uint32_t core_id) { REG_WRITE(BUS_MONITOR_CORE_0_INTR_CLR_REG, BUS_MONITOR_SP_SPILL_BITS); } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_set_min(__attribute__((unused)) uint32_t core_id, uint32_t min) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_set_min(__attribute__((unused)) uint32_t core_id, uint32_t min) { REG_WRITE(BUS_MONITOR_CORE_0_SP_MIN_REG, min); } -FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_min(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline uint32_t assist_debug_ll_sp_spill_get_min(__attribute__((unused)) uint32_t core_id) { return REG_READ(BUS_MONITOR_CORE_0_SP_MIN_REG); } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_set_max(__attribute__((unused)) uint32_t core_id, uint32_t max) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_set_max(__attribute__((unused)) uint32_t core_id, uint32_t max) { REG_WRITE(BUS_MONITOR_CORE_0_SP_MAX_REG, max); } -FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_max(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline uint32_t assist_debug_ll_sp_spill_get_max(__attribute__((unused)) uint32_t core_id) { return REG_READ(BUS_MONITOR_CORE_0_SP_MAX_REG); } -FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_pc(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline uint32_t assist_debug_ll_sp_spill_get_pc(__attribute__((unused)) uint32_t core_id) { return REG_READ(BUS_MONITOR_CORE_0_SP_PC_REG); } -FORCE_INLINE_ATTR void assist_debug_ll_enable_pc_recording(uint32_t core_id, bool enable) +__attribute__((always_inline)) +static inline void assist_debug_ll_enable_pc_recording(uint32_t core_id, bool enable) { } -FORCE_INLINE_ATTR void assist_debug_ll_enable_bus_clock(__attribute__((unused)) uint32_t core_id, bool enable) +__attribute__((always_inline)) +static inline void assist_debug_ll_enable_bus_clock(__attribute__((unused)) uint32_t core_id, bool enable) { PCR.assist_conf.assist_clk_en = enable; } -FORCE_INLINE_ATTR void assist_debug_ll_reset_register(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_reset_register(__attribute__((unused)) uint32_t core_id) { PCR.assist_conf.assist_rst_en = true; PCR.assist_conf.assist_rst_en = false; } -FORCE_INLINE_ATTR bool assist_debug_ll_is_debugger_active(void) +__attribute__((always_inline)) +static inline bool assist_debug_ll_is_debugger_active(void) { return REG_GET_BIT(BUS_MONITOR_CORE_0_DEBUG_MODE_REG, BUS_MONITOR_CORE_0_DEBUG_MODULE_ACTIVE); } diff --git a/components/hal/esp32h2/include/hal/assist_debug_ll.h b/components/esp_hal_debug_assist/esp32h2/include/hal/assist_debug_ll.h similarity index 66% rename from components/hal/esp32h2/include/hal/assist_debug_ll.h rename to components/esp_hal_debug_assist/esp32h2/include/hal/assist_debug_ll.h index 9c559815cc4..1231172b3ef 100644 --- a/components/hal/esp32h2/include/hal/assist_debug_ll.h +++ b/components/esp_hal_debug_assist/esp32h2/include/hal/assist_debug_ll.h @@ -4,11 +4,10 @@ * SPDX-License-Identifier: Apache-2.0 */ -// The LL layer for DEBUG_ASSIST peripheral - #pragma once #include "soc/assist_debug_reg.h" + #define ASSIST_DEBUG_SP_SPILL_BITS (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA | ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA) #define ASSIST_DEBUG_CORE_0_MONITOR_REG ASSIST_DEBUG_CORE_0_INTR_ENA_REG @@ -16,7 +15,6 @@ #include #include -#include "esp_attr.h" #include "hal/assert.h" #include "soc/pcr_struct.h" @@ -59,77 +57,92 @@ extern "C" { /* These functions are optimized and designed for internal usage. * So, the API may differ from general ll layer pattern */ -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_monitor_enable(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_monitor_enable(__attribute__((unused)) uint32_t core_id) { REG_SET_BIT(ASSIST_DEBUG_CORE_0_INTR_ENA_REG, ASSIST_DEBUG_SP_SPILL_BITS); } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_monitor_disable(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_monitor_disable(__attribute__((unused)) uint32_t core_id) { REG_CLR_BIT(ASSIST_DEBUG_CORE_0_INTR_ENA_REG, ASSIST_DEBUG_SP_SPILL_BITS); } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_interrupt_enable(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_interrupt_enable(__attribute__((unused)) uint32_t core_id) { REG_SET_BIT(ASSIST_DEBUG_CORE_0_INTR_RLS_REG, ASSIST_DEBUG_SP_SPILL_BITS); } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_interrupt_disable(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_interrupt_disable(__attribute__((unused)) uint32_t core_id) { REG_CLR_BIT(ASSIST_DEBUG_CORE_0_INTR_RLS_REG, ASSIST_DEBUG_SP_SPILL_BITS); } -FORCE_INLINE_ATTR bool assist_debug_ll_sp_spill_is_fired(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline bool assist_debug_ll_sp_spill_is_fired(__attribute__((unused)) uint32_t core_id) { return REG_READ(ASSIST_DEBUG_CORE_0_INTR_RAW_REG) & ASSIST_DEBUG_SP_SPILL_BITS; } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_interrupt_clear(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_interrupt_clear(__attribute__((unused)) uint32_t core_id) { REG_WRITE(ASSIST_DEBUG_CORE_0_INTR_CLR_REG, ASSIST_DEBUG_SP_SPILL_BITS); } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_set_min(__attribute__((unused)) uint32_t core_id, uint32_t min) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_set_min(__attribute__((unused)) uint32_t core_id, uint32_t min) { REG_WRITE(ASSIST_DEBUG_CORE_0_SP_MIN_REG, min); } -FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_min(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline uint32_t assist_debug_ll_sp_spill_get_min(__attribute__((unused)) uint32_t core_id) { return REG_READ(ASSIST_DEBUG_CORE_0_SP_MIN_REG); } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_set_max(__attribute__((unused)) uint32_t core_id, uint32_t max) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_set_max(__attribute__((unused)) uint32_t core_id, uint32_t max) { REG_WRITE(ASSIST_DEBUG_CORE_0_SP_MAX_REG, max); } -FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_max(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline uint32_t assist_debug_ll_sp_spill_get_max(__attribute__((unused)) uint32_t core_id) { return REG_READ(ASSIST_DEBUG_CORE_0_SP_MAX_REG); } -FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_pc(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline uint32_t assist_debug_ll_sp_spill_get_pc(__attribute__((unused)) uint32_t core_id) { return REG_READ(ASSIST_DEBUG_CORE_0_SP_PC_REG); } -FORCE_INLINE_ATTR void assist_debug_ll_enable_pc_recording(uint32_t core_id, bool enable) +__attribute__((always_inline)) +static inline void assist_debug_ll_enable_pc_recording(uint32_t core_id, bool enable) { } -FORCE_INLINE_ATTR void assist_debug_ll_enable_bus_clock(__attribute__((unused)) uint32_t core_id, bool enable) +__attribute__((always_inline)) +static inline void assist_debug_ll_enable_bus_clock(__attribute__((unused)) uint32_t core_id, bool enable) { PCR.assist_conf.assist_clk_en = enable; } -FORCE_INLINE_ATTR void assist_debug_ll_reset_register(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_reset_register(__attribute__((unused)) uint32_t core_id) { PCR.assist_conf.assist_rst_en = true; PCR.assist_conf.assist_rst_en = false; } -FORCE_INLINE_ATTR bool assist_debug_ll_is_debugger_active(void) +__attribute__((always_inline)) +static inline bool assist_debug_ll_is_debugger_active(void) { return REG_GET_BIT(ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG, ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE); } diff --git a/components/hal/esp32h21/include/hal/assist_debug_ll.h b/components/esp_hal_debug_assist/esp32h21/include/hal/assist_debug_ll.h similarity index 66% rename from components/hal/esp32h21/include/hal/assist_debug_ll.h rename to components/esp_hal_debug_assist/esp32h21/include/hal/assist_debug_ll.h index c67084881b0..06dc75cf944 100644 --- a/components/hal/esp32h21/include/hal/assist_debug_ll.h +++ b/components/esp_hal_debug_assist/esp32h21/include/hal/assist_debug_ll.h @@ -4,11 +4,10 @@ * SPDX-License-Identifier: Apache-2.0 */ -// The LL layer for DEBUG_ASSIST peripheral - #pragma once #include "soc/assist_debug_reg.h" + #define ASSIST_DEBUG_SP_SPILL_BITS (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA | ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA) #define ASSIST_DEBUG_CORE_0_MONITOR_REG ASSIST_DEBUG_CORE_0_INTR_ENA_REG @@ -16,7 +15,6 @@ #include #include -#include "esp_attr.h" #include "hal/assert.h" #include "soc/pcr_struct.h" @@ -59,77 +57,92 @@ extern "C" { /* These functions are optimized and designed for internal usage. * So, the API may differ from general ll layer pattern */ -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_monitor_enable(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_monitor_enable(__attribute__((unused)) uint32_t core_id) { REG_SET_BIT(ASSIST_DEBUG_CORE_0_INTR_ENA_REG, ASSIST_DEBUG_SP_SPILL_BITS); } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_monitor_disable(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_monitor_disable(__attribute__((unused)) uint32_t core_id) { REG_CLR_BIT(ASSIST_DEBUG_CORE_0_INTR_ENA_REG, ASSIST_DEBUG_SP_SPILL_BITS); } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_interrupt_enable(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_interrupt_enable(__attribute__((unused)) uint32_t core_id) { REG_SET_BIT(ASSIST_DEBUG_CORE_0_INTR_RLS_REG, ASSIST_DEBUG_SP_SPILL_BITS); } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_interrupt_disable(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_interrupt_disable(__attribute__((unused)) uint32_t core_id) { REG_CLR_BIT(ASSIST_DEBUG_CORE_0_INTR_RLS_REG, ASSIST_DEBUG_SP_SPILL_BITS); } -FORCE_INLINE_ATTR bool assist_debug_ll_sp_spill_is_fired(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline bool assist_debug_ll_sp_spill_is_fired(__attribute__((unused)) uint32_t core_id) { return REG_READ(ASSIST_DEBUG_CORE_0_INTR_RAW_REG) & ASSIST_DEBUG_SP_SPILL_BITS; } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_interrupt_clear(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_interrupt_clear(__attribute__((unused)) uint32_t core_id) { REG_WRITE(ASSIST_DEBUG_CORE_0_INTR_CLR_REG, ASSIST_DEBUG_SP_SPILL_BITS); } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_set_min(__attribute__((unused)) uint32_t core_id, uint32_t min) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_set_min(__attribute__((unused)) uint32_t core_id, uint32_t min) { REG_WRITE(ASSIST_DEBUG_CORE_0_SP_MIN_REG, min); } -FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_min(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline uint32_t assist_debug_ll_sp_spill_get_min(__attribute__((unused)) uint32_t core_id) { return REG_READ(ASSIST_DEBUG_CORE_0_SP_MIN_REG); } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_set_max(__attribute__((unused)) uint32_t core_id, uint32_t max) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_set_max(__attribute__((unused)) uint32_t core_id, uint32_t max) { REG_WRITE(ASSIST_DEBUG_CORE_0_SP_MAX_REG, max); } -FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_max(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline uint32_t assist_debug_ll_sp_spill_get_max(__attribute__((unused)) uint32_t core_id) { return REG_READ(ASSIST_DEBUG_CORE_0_SP_MAX_REG); } -FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_pc(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline uint32_t assist_debug_ll_sp_spill_get_pc(__attribute__((unused)) uint32_t core_id) { return REG_READ(ASSIST_DEBUG_CORE_0_SP_PC_REG); } -FORCE_INLINE_ATTR void assist_debug_ll_enable_pc_recording(uint32_t core_id, bool enable) +__attribute__((always_inline)) +static inline void assist_debug_ll_enable_pc_recording(uint32_t core_id, bool enable) { } -FORCE_INLINE_ATTR void assist_debug_ll_enable_bus_clock(__attribute__((unused)) uint32_t core_id, bool enable) +__attribute__((always_inline)) +static inline void assist_debug_ll_enable_bus_clock(__attribute__((unused)) uint32_t core_id, bool enable) { PCR.assist_conf.assist_clk_en = enable; } -FORCE_INLINE_ATTR void assist_debug_ll_reset_register(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_reset_register(__attribute__((unused)) uint32_t core_id) { PCR.assist_conf.assist_rst_en = true; PCR.assist_conf.assist_rst_en = false; } -FORCE_INLINE_ATTR bool assist_debug_ll_is_debugger_active(void) +__attribute__((always_inline)) +static inline bool assist_debug_ll_is_debugger_active(void) { return REG_GET_BIT(ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG, ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE); } diff --git a/components/hal/esp32h4/include/hal/assist_debug_ll.h b/components/esp_hal_debug_assist/esp32h4/include/hal/assist_debug_ll.h similarity index 76% rename from components/hal/esp32h4/include/hal/assist_debug_ll.h rename to components/esp_hal_debug_assist/esp32h4/include/hal/assist_debug_ll.h index 8d55b9ba2a5..c7dbb50702a 100644 --- a/components/hal/esp32h4/include/hal/assist_debug_ll.h +++ b/components/esp_hal_debug_assist/esp32h4/include/hal/assist_debug_ll.h @@ -4,8 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ -// The LL layer for DEBUG_ASSIST peripheral - #pragma once #include "soc/assist_debug_reg.h" @@ -14,7 +12,6 @@ #include #include -#include "esp_attr.h" #include "soc/pcr_struct.h" #include "soc/bus_monitor_struct.h" #include "soc/lp_clkrst_struct.h" @@ -28,7 +25,8 @@ extern "C" { * */ -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_monitor_enable(uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_monitor_enable(uint32_t core_id) { if (core_id) { BUS_MONITOR.monitor_core_1_montr_ena.monitor_core_1_sp_spill_min_ena = 1; @@ -39,7 +37,8 @@ FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_monitor_enable(uint32_t core_id) } } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_monitor_disable(uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_monitor_disable(uint32_t core_id) { if (core_id) { BUS_MONITOR.monitor_core_1_montr_ena.monitor_core_1_sp_spill_min_ena = 0; @@ -50,7 +49,8 @@ FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_monitor_disable(uint32_t core_id } } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_interrupt_enable(uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_interrupt_enable(uint32_t core_id) { if (core_id) { BUS_MONITOR.monitor_core_1_intr_ena.monitor_core_1_sp_spill_min_intr_ena = 1; @@ -61,7 +61,8 @@ FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_interrupt_enable(uint32_t core_i } } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_interrupt_disable(uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_interrupt_disable(uint32_t core_id) { if (core_id) { BUS_MONITOR.monitor_core_1_intr_ena.monitor_core_1_sp_spill_min_intr_ena = 0; @@ -72,7 +73,8 @@ FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_interrupt_disable(uint32_t core_ } } -FORCE_INLINE_ATTR bool assist_debug_ll_sp_spill_is_fired(uint32_t core_id) +__attribute__((always_inline)) +static inline bool assist_debug_ll_sp_spill_is_fired(uint32_t core_id) { if (core_id) { return BUS_MONITOR.monitor_core_1_intr_raw.monitor_core_1_sp_spill_min_raw || BUS_MONITOR.monitor_core_1_intr_raw.monitor_core_1_sp_spill_max_raw; @@ -81,7 +83,8 @@ FORCE_INLINE_ATTR bool assist_debug_ll_sp_spill_is_fired(uint32_t core_id) } } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_interrupt_clear(uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_interrupt_clear(uint32_t core_id) { if (core_id) { BUS_MONITOR.monitor_core_1_intr_clr.monitor_core_1_sp_spill_min_clr = 1; @@ -92,7 +95,8 @@ FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_interrupt_clear(uint32_t core_id } } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_set_min(uint32_t core_id, uint32_t min) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_set_min(uint32_t core_id, uint32_t min) { if (core_id) { BUS_MONITOR.monitor_core_1_sp_min.monitor_core_1_sp_min = min; @@ -101,7 +105,8 @@ FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_set_min(uint32_t core_id, uint32 } } -FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_min(uint32_t core_id) +__attribute__((always_inline)) +static inline uint32_t assist_debug_ll_sp_spill_get_min(uint32_t core_id) { if (core_id) { return BUS_MONITOR.monitor_core_1_sp_min.monitor_core_1_sp_min; @@ -110,7 +115,8 @@ FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_min(uint32_t core_id) } } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_set_max(uint32_t core_id, uint32_t max) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_set_max(uint32_t core_id, uint32_t max) { if (core_id) { BUS_MONITOR.monitor_core_1_sp_max.monitor_core_1_sp_max = max; @@ -119,7 +125,8 @@ FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_set_max(uint32_t core_id, uint32 } } -FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_max(uint32_t core_id) +__attribute__((always_inline)) +static inline uint32_t assist_debug_ll_sp_spill_get_max(uint32_t core_id) { if (core_id) { return BUS_MONITOR.monitor_core_1_sp_max.monitor_core_1_sp_max; @@ -128,7 +135,8 @@ FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_max(uint32_t core_id) } } -FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_pc(uint32_t core_id) +__attribute__((always_inline)) +static inline uint32_t assist_debug_ll_sp_spill_get_pc(uint32_t core_id) { if (core_id) { return BUS_MONITOR.monitor_core_1_sp_pc.monitor_core_1_sp_pc; @@ -137,7 +145,8 @@ FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_pc(uint32_t core_id) } } -FORCE_INLINE_ATTR void assist_debug_ll_enable_pc_recording(uint32_t core_id, bool enable) +__attribute__((always_inline)) +static inline void assist_debug_ll_enable_pc_recording(uint32_t core_id, bool enable) { if (core_id) { BUS_MONITOR.monitor_core_1_rcd_en.monitor_core_1_rcd_pdebugen = enable; @@ -148,7 +157,8 @@ FORCE_INLINE_ATTR void assist_debug_ll_enable_pc_recording(uint32_t core_id, boo } } -FORCE_INLINE_ATTR void assist_debug_ll_enable_bus_clock(uint32_t core_id, bool enable) +__attribute__((always_inline)) +static inline void assist_debug_ll_enable_bus_clock(uint32_t core_id, bool enable) { if (core_id) { PCR.assist_conf.assist1_clk_en = enable; @@ -157,7 +167,8 @@ FORCE_INLINE_ATTR void assist_debug_ll_enable_bus_clock(uint32_t core_id, bool e } } -FORCE_INLINE_ATTR void assist_debug_ll_reset_register(uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_reset_register(uint32_t core_id) { if (core_id) { PCR.assist_conf.assist1_rst_en = true; @@ -168,12 +179,14 @@ FORCE_INLINE_ATTR void assist_debug_ll_reset_register(uint32_t core_id) } } -FORCE_INLINE_ATTR bool assist_debug_ll_is_debugger_active(void) +__attribute__((always_inline)) +static inline bool assist_debug_ll_is_debugger_active(void) { return BUS_MONITOR.monitor_core_0_debug_mode.monitor_core_0_debug_module_active; } -FORCE_INLINE_ATTR void assist_debug_ll_lockup_monitor_enable(uint32_t core_id, bool enable) +__attribute__((always_inline)) +static inline void assist_debug_ll_lockup_monitor_enable(uint32_t core_id, bool enable) { if (core_id) { BUS_MONITOR.monitor_core_1_montr_ena.monitor_core_1_trace_lockup_ena = enable; @@ -184,7 +197,8 @@ FORCE_INLINE_ATTR void assist_debug_ll_lockup_monitor_enable(uint32_t core_id, b // trap_idx: 0 = latest trap, 1 = previous trap // MCause for the exception -FORCE_INLINE_ATTR uint32_t assist_debug_ll_lockup_get_cause(uint32_t core_id, int trap_idx) +__attribute__((always_inline)) +static inline uint32_t assist_debug_ll_lockup_get_cause(uint32_t core_id, int trap_idx) { if (core_id) { return trap_idx ? BUS_MONITOR.monitor_core_1_trace_lockup_cause_1.monitor_core_1_trace_lockup_recording_cause_1 @@ -195,7 +209,8 @@ FORCE_INLINE_ATTR uint32_t assist_debug_ll_lockup_get_cause(uint32_t core_id, in } } -FORCE_INLINE_ATTR uint32_t assist_debug_ll_lockup_get_tval(uint32_t core_id, int trap_idx) +__attribute__((always_inline)) +static inline uint32_t assist_debug_ll_lockup_get_tval(uint32_t core_id, int trap_idx) { if (core_id) { return trap_idx ? BUS_MONITOR.monitor_core_1_trace_lockup_tval_1.monitor_core_1_trace_lockup_recording_tval_1 @@ -206,7 +221,8 @@ FORCE_INLINE_ATTR uint32_t assist_debug_ll_lockup_get_tval(uint32_t core_id, int } } -FORCE_INLINE_ATTR uint32_t assist_debug_ll_lockup_get_iaddr(uint32_t core_id, int trap_idx) +__attribute__((always_inline)) +static inline uint32_t assist_debug_ll_lockup_get_iaddr(uint32_t core_id, int trap_idx) { if (core_id) { return trap_idx ? BUS_MONITOR.monitor_core_1_trace_lockup_iaddr_1.monitor_core_1_trace_lockup_recording_iaddr_1 @@ -217,7 +233,8 @@ FORCE_INLINE_ATTR uint32_t assist_debug_ll_lockup_get_iaddr(uint32_t core_id, in } } -FORCE_INLINE_ATTR uint32_t assist_debug_ll_lockup_get_priv(uint32_t core_id, int trap_idx) +__attribute__((always_inline)) +static inline uint32_t assist_debug_ll_lockup_get_priv(uint32_t core_id, int trap_idx) { if (core_id) { return trap_idx ? BUS_MONITOR.monitor_core_1_trace_lockup_priv_1.monitor_core_1_trace_lockup_recording_priv_1 @@ -231,7 +248,8 @@ FORCE_INLINE_ATTR uint32_t assist_debug_ll_lockup_get_priv(uint32_t core_id, int /* Enable the hardware lockup reset for the given core via LP_CLKRST. * This controls whether a CPU lockup (exception inside exception handler) triggers * a system reset. Defaults to 1 on H4 but must be set explicitly to be safe. */ -FORCE_INLINE_ATTR void assist_debug_ll_lockup_reset_enable(uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_lockup_reset_enable(uint32_t core_id) { if (core_id) { LP_CLKRST.cpu_core1_reset.hpcore1_lockup_reset_en = 1; diff --git a/components/hal/esp32p4/include/hal/assist_debug_ll.h b/components/esp_hal_debug_assist/esp32p4/include/hal/assist_debug_ll.h similarity index 75% rename from components/hal/esp32p4/include/hal/assist_debug_ll.h rename to components/esp_hal_debug_assist/esp32p4/include/hal/assist_debug_ll.h index bc7cf57ea27..9d8d1fa90a2 100644 --- a/components/hal/esp32p4/include/hal/assist_debug_ll.h +++ b/components/esp_hal_debug_assist/esp32p4/include/hal/assist_debug_ll.h @@ -4,11 +4,10 @@ * SPDX-License-Identifier: Apache-2.0 */ -// The LL layer for DEBUG_ASSIST peripheral - #pragma once #include "soc/assist_debug_reg.h" + #define ASSIST_DEBUG_SP_SPILL_BITS (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA | ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA) #define ASSIST_DEBUG_CORE_0_MONITOR_REG ASSIST_DEBUG_CORE_0_INTR_ENA_REG #define ASSIST_DEBUG_CORE_1_MONITOR_REG ASSIST_DEBUG_CORE_1_INTR_ENA_REG @@ -17,7 +16,6 @@ #include #include -#include "esp_attr.h" #include "hal/assert.h" #include "soc/hp_sys_clkrst_struct.h" #include "soc/soc_caps.h" @@ -61,62 +59,74 @@ extern "C" { /* These functions are optimized and designed for internal usage. * So, the API may differ from general ll layer pattern */ -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_monitor_enable(uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_monitor_enable(uint32_t core_id) { REG_SET_BIT(core_id ? ASSIST_DEBUG_CORE_1_INTR_ENA_REG : ASSIST_DEBUG_CORE_0_INTR_ENA_REG, ASSIST_DEBUG_SP_SPILL_BITS); } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_monitor_disable(uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_monitor_disable(uint32_t core_id) { REG_CLR_BIT(core_id ? ASSIST_DEBUG_CORE_1_INTR_ENA_REG : ASSIST_DEBUG_CORE_0_INTR_ENA_REG, ASSIST_DEBUG_SP_SPILL_BITS); } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_interrupt_enable(uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_interrupt_enable(uint32_t core_id) { REG_SET_BIT(core_id ? ASSIST_DEBUG_CORE_1_INTR_RLS_REG : ASSIST_DEBUG_CORE_0_INTR_RLS_REG, ASSIST_DEBUG_SP_SPILL_BITS); } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_interrupt_disable(uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_interrupt_disable(uint32_t core_id) { REG_CLR_BIT(core_id ? ASSIST_DEBUG_CORE_1_INTR_RLS_REG : ASSIST_DEBUG_CORE_0_INTR_RLS_REG, ASSIST_DEBUG_SP_SPILL_BITS); } -FORCE_INLINE_ATTR bool assist_debug_ll_sp_spill_is_fired(uint32_t core_id) +__attribute__((always_inline)) +static inline bool assist_debug_ll_sp_spill_is_fired(uint32_t core_id) { return REG_READ(core_id ? ASSIST_DEBUG_CORE_1_INTR_RAW_REG : ASSIST_DEBUG_CORE_0_INTR_RAW_REG) & ASSIST_DEBUG_SP_SPILL_BITS; } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_interrupt_clear(uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_interrupt_clear(uint32_t core_id) { REG_WRITE(core_id ? ASSIST_DEBUG_CORE_1_INTR_CLR_REG : ASSIST_DEBUG_CORE_0_INTR_CLR_REG, ASSIST_DEBUG_SP_SPILL_BITS); } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_set_min(uint32_t core_id, uint32_t min) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_set_min(uint32_t core_id, uint32_t min) { REG_WRITE(core_id ? ASSIST_DEBUG_CORE_1_SP_MIN_REG : ASSIST_DEBUG_CORE_0_SP_MIN_REG, min); } -FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_min(uint32_t core_id) +__attribute__((always_inline)) +static inline uint32_t assist_debug_ll_sp_spill_get_min(uint32_t core_id) { return REG_READ(core_id ? ASSIST_DEBUG_CORE_1_SP_MIN_REG : ASSIST_DEBUG_CORE_0_SP_MIN_REG); } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_set_max(uint32_t core_id, uint32_t max) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_set_max(uint32_t core_id, uint32_t max) { REG_WRITE(core_id ? ASSIST_DEBUG_CORE_1_SP_MAX_REG : ASSIST_DEBUG_CORE_0_SP_MAX_REG, max); } -FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_max(uint32_t core_id) +__attribute__((always_inline)) +static inline uint32_t assist_debug_ll_sp_spill_get_max(uint32_t core_id) { return REG_READ(core_id ? ASSIST_DEBUG_CORE_1_SP_MAX_REG : ASSIST_DEBUG_CORE_0_SP_MAX_REG); } -FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_pc(uint32_t core_id) +__attribute__((always_inline)) +static inline uint32_t assist_debug_ll_sp_spill_get_pc(uint32_t core_id) { return REG_READ(core_id ? ASSIST_DEBUG_CORE_1_SP_PC_REG : ASSIST_DEBUG_CORE_0_SP_PC_REG); } -FORCE_INLINE_ATTR void assist_debug_ll_enable_pc_recording(uint32_t core_id, bool enable) +__attribute__((always_inline)) +static inline void assist_debug_ll_enable_pc_recording(uint32_t core_id, bool enable) { uint32_t reg = core_id ? ASSIST_DEBUG_CORE_1_RCD_EN_REG : ASSIST_DEBUG_CORE_0_RCD_EN_REG; uint32_t bits = ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN | ASSIST_DEBUG_CORE_0_RCD_RECORDEN; @@ -128,7 +138,8 @@ FORCE_INLINE_ATTR void assist_debug_ll_enable_pc_recording(uint32_t core_id, boo } } -FORCE_INLINE_ATTR void _assist_debug_ll_enable_bus_clock(__attribute__((unused)) uint32_t core_id, bool enable) +__attribute__((always_inline)) +static inline void _assist_debug_ll_enable_bus_clock(__attribute__((unused)) uint32_t core_id, bool enable) { HP_SYS_CLKRST.soc_clk_ctrl0.reg_busmon_cpu_clk_en = enable; REG_SET_FIELD(ASSIST_DEBUG_CLOCK_GATE_REG, ASSIST_DEBUG_CLK_EN, enable); @@ -136,7 +147,8 @@ FORCE_INLINE_ATTR void _assist_debug_ll_enable_bus_clock(__attribute__((unused)) #define assist_debug_ll_enable_bus_clock(...) \ (void)__DECLARE_RCC_ATOMIC_ENV; _assist_debug_ll_enable_bus_clock(__VA_ARGS__) -FORCE_INLINE_ATTR void _assist_debug_ll_reset_register(__attribute__((unused)) uint32_t core_id) +__attribute__((always_inline)) +static inline void _assist_debug_ll_reset_register(__attribute__((unused)) uint32_t core_id) { /* esp32p4 has no assist_debug reset register: disable & clear interrupts manually. */ for (int i = 0; i < SOC_CPU_CORES_NUM; i++) { @@ -149,7 +161,8 @@ FORCE_INLINE_ATTR void _assist_debug_ll_reset_register(__attribute__((unused)) u #define assist_debug_ll_reset_register(...) \ (void)__DECLARE_RCC_ATOMIC_ENV; _assist_debug_ll_reset_register(__VA_ARGS__) -FORCE_INLINE_ATTR bool assist_debug_ll_is_debugger_active(void) +__attribute__((always_inline)) +static inline bool assist_debug_ll_is_debugger_active(void) { return REG_GET_BIT(ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG, ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE); } diff --git a/components/hal/esp32p4/include/hal/debug_probe_ll.h b/components/esp_hal_debug_assist/esp32p4/include/hal/debug_probe_ll.h similarity index 100% rename from components/hal/esp32p4/include/hal/debug_probe_ll.h rename to components/esp_hal_debug_assist/esp32p4/include/hal/debug_probe_ll.h diff --git a/components/hal/esp32p4/include/hal/riscv_trace_ll.h b/components/esp_hal_debug_assist/esp32p4/include/hal/riscv_trace_ll.h similarity index 94% rename from components/hal/esp32p4/include/hal/riscv_trace_ll.h rename to components/esp_hal_debug_assist/esp32p4/include/hal/riscv_trace_ll.h index 71b85feb29d..afc84f0ee6f 100644 --- a/components/hal/esp32p4/include/hal/riscv_trace_ll.h +++ b/components/esp_hal_debug_assist/esp32p4/include/hal/riscv_trace_ll.h @@ -30,19 +30,14 @@ static inline trace_dev_t *riscv_trace_ll_get_hw(int core) *--------------------------------------------------------------------------*/ /** @brief Enable or disable the common TRACE CPU and system clocks. */ -static inline void _riscv_trace_ll_enable_bus_clock(bool enable) +static inline void riscv_trace_ll_enable_bus_clock(bool enable) { HP_SYS_CLKRST.soc_clk_ctrl0.reg_trace_cpu_clk_en = enable; HP_SYS_CLKRST.soc_clk_ctrl0.reg_trace_sys_clk_en = enable; } -#define riscv_trace_ll_enable_bus_clock(...) do { \ - (void)__DECLARE_RCC_ATOMIC_ENV; \ - _riscv_trace_ll_enable_bus_clock(__VA_ARGS__); \ -} while (0) - /** @brief Assert and release the reset of the given encoder core. */ -static inline void _riscv_trace_ll_reset_register(int core) +static inline void riscv_trace_ll_reset_register(int core) { if (core == 0) { HP_SYS_CLKRST.hp_rst_en0.reg_rst_en_coretrace0 = 1; @@ -53,11 +48,6 @@ static inline void _riscv_trace_ll_reset_register(int core) } } -#define riscv_trace_ll_reset_register(...) do { \ - (void)__DECLARE_RCC_ATOMIC_ENV; \ - _riscv_trace_ll_reset_register(__VA_ARGS__); \ - } while (0) - /** @brief Enable the per-module register clock gate. */ static inline void riscv_trace_ll_enable_module_clock(trace_dev_t *hw, bool enable) { diff --git a/components/hal/esp32s2/include/hal/trace_ll.h b/components/esp_hal_debug_assist/esp32s2/include/hal/xtensa_trace_ll.h similarity index 100% rename from components/hal/esp32s2/include/hal/trace_ll.h rename to components/esp_hal_debug_assist/esp32s2/include/hal/xtensa_trace_ll.h diff --git a/components/hal/esp32s3/include/hal/trace_ll.h b/components/esp_hal_debug_assist/esp32s3/include/hal/xtensa_trace_ll.h similarity index 86% rename from components/hal/esp32s3/include/hal/trace_ll.h rename to components/esp_hal_debug_assist/esp32s3/include/hal/xtensa_trace_ll.h index df2afeacb9c..1af77727bce 100644 --- a/components/hal/esp32s3/include/hal/trace_ll.h +++ b/components/esp_hal_debug_assist/esp32s3/include/hal/xtensa_trace_ll.h @@ -1,12 +1,12 @@ /* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #pragma once -#include +#include #include "soc/dport_reg.h" #include "soc/tracemem_config.h" diff --git a/components/hal/esp32s31/include/hal/assist_debug_ll.h b/components/esp_hal_debug_assist/esp32s31/include/hal/assist_debug_ll.h similarity index 74% rename from components/hal/esp32s31/include/hal/assist_debug_ll.h rename to components/esp_hal_debug_assist/esp32s31/include/hal/assist_debug_ll.h index 23c7e91e77c..5ef1143afaa 100644 --- a/components/hal/esp32s31/include/hal/assist_debug_ll.h +++ b/components/esp_hal_debug_assist/esp32s31/include/hal/assist_debug_ll.h @@ -4,8 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ -// The LL layer for DEBUG_ASSIST peripheral - #pragma once #include "soc/assist_debug_reg.h" @@ -14,7 +12,6 @@ #include #include -#include "esp_attr.h" #include "soc/hp_sys_clkrst_struct.h" #include "soc/bus_monitor_struct.h" #include "soc/lp_clkrst_struct.h" @@ -28,7 +25,8 @@ extern "C" { * */ -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_monitor_enable(uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_monitor_enable(uint32_t core_id) { if (core_id) { BUS_MONITOR.core_1_montr_ena.core_1_sp_spill_min_ena = 1; @@ -39,7 +37,8 @@ FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_monitor_enable(uint32_t core_id) } } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_monitor_disable(uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_monitor_disable(uint32_t core_id) { if (core_id) { BUS_MONITOR.core_1_montr_ena.core_1_sp_spill_min_ena = 0; @@ -50,7 +49,8 @@ FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_monitor_disable(uint32_t core_id } } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_interrupt_enable(uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_interrupt_enable(uint32_t core_id) { if (core_id) { BUS_MONITOR.core_1_intr_ena.core_1_sp_spill_min_intr_ena = 1; @@ -61,7 +61,8 @@ FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_interrupt_enable(uint32_t core_i } } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_interrupt_disable(uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_interrupt_disable(uint32_t core_id) { if (core_id) { BUS_MONITOR.core_1_intr_ena.core_1_sp_spill_min_intr_ena = 0; @@ -72,7 +73,8 @@ FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_interrupt_disable(uint32_t core_ } } -FORCE_INLINE_ATTR bool assist_debug_ll_sp_spill_is_fired(uint32_t core_id) +__attribute__((always_inline)) +static inline bool assist_debug_ll_sp_spill_is_fired(uint32_t core_id) { if (core_id) { return BUS_MONITOR.core_1_intr_raw.core_1_sp_spill_min_raw || BUS_MONITOR.core_1_intr_raw.core_1_sp_spill_max_raw; @@ -81,7 +83,8 @@ FORCE_INLINE_ATTR bool assist_debug_ll_sp_spill_is_fired(uint32_t core_id) } } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_interrupt_clear(uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_interrupt_clear(uint32_t core_id) { if (core_id) { BUS_MONITOR.core_1_intr_clr.core_1_sp_spill_min_clr = 1; @@ -92,7 +95,8 @@ FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_interrupt_clear(uint32_t core_id } } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_set_min(uint32_t core_id, uint32_t min) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_set_min(uint32_t core_id, uint32_t min) { if (core_id) { BUS_MONITOR.core_1_sp_min.core_1_sp_min = min; @@ -101,7 +105,8 @@ FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_set_min(uint32_t core_id, uint32 } } -FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_min(uint32_t core_id) +__attribute__((always_inline)) +static inline uint32_t assist_debug_ll_sp_spill_get_min(uint32_t core_id) { if (core_id) { return BUS_MONITOR.core_1_sp_min.core_1_sp_min; @@ -110,7 +115,8 @@ FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_min(uint32_t core_id) } } -FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_set_max(uint32_t core_id, uint32_t max) +__attribute__((always_inline)) +static inline void assist_debug_ll_sp_spill_set_max(uint32_t core_id, uint32_t max) { if (core_id) { BUS_MONITOR.core_1_sp_max.core_1_sp_max = max; @@ -119,7 +125,8 @@ FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_set_max(uint32_t core_id, uint32 } } -FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_max(uint32_t core_id) +__attribute__((always_inline)) +static inline uint32_t assist_debug_ll_sp_spill_get_max(uint32_t core_id) { if (core_id) { return BUS_MONITOR.core_1_sp_max.core_1_sp_max; @@ -128,7 +135,8 @@ FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_max(uint32_t core_id) } } -FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_pc(uint32_t core_id) +__attribute__((always_inline)) +static inline uint32_t assist_debug_ll_sp_spill_get_pc(uint32_t core_id) { if (core_id) { return BUS_MONITOR.core_1_sp_pc.core_1_sp_pc; @@ -137,7 +145,8 @@ FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_pc(uint32_t core_id) } } -FORCE_INLINE_ATTR void assist_debug_ll_enable_pc_recording(uint32_t core_id, bool enable) +__attribute__((always_inline)) +static inline void assist_debug_ll_enable_pc_recording(uint32_t core_id, bool enable) { if (core_id) { BUS_MONITOR.core_1_rcd_en.core_1_rcd_pdebugen = enable; @@ -148,7 +157,8 @@ FORCE_INLINE_ATTR void assist_debug_ll_enable_pc_recording(uint32_t core_id, boo } } -FORCE_INLINE_ATTR void assist_debug_ll_enable_bus_clock(uint32_t core_id, bool enable) +__attribute__((always_inline)) +static inline void assist_debug_ll_enable_bus_clock(uint32_t core_id, bool enable) { if (core_id) { HP_SYS_CLKRST.busmon_ctrl0.reg_busmon_core1_clk_en = enable; @@ -157,7 +167,8 @@ FORCE_INLINE_ATTR void assist_debug_ll_enable_bus_clock(uint32_t core_id, bool e } } -FORCE_INLINE_ATTR void assist_debug_ll_reset_register(uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_reset_register(uint32_t core_id) { if (core_id) { HP_SYS_CLKRST.busmon_ctrl0.reg_busmon_core1_rst_en = true; @@ -168,12 +179,14 @@ FORCE_INLINE_ATTR void assist_debug_ll_reset_register(uint32_t core_id) } } -FORCE_INLINE_ATTR bool assist_debug_ll_is_debugger_active(void) +__attribute__((always_inline)) +static inline bool assist_debug_ll_is_debugger_active(void) { return BUS_MONITOR.core_0_debug_mode.core_0_debug_module_active; } -FORCE_INLINE_ATTR void assist_debug_ll_lockup_monitor_enable(uint32_t core_id, bool enable) +__attribute__((always_inline)) +static inline void assist_debug_ll_lockup_monitor_enable(uint32_t core_id, bool enable) { if (core_id) { BUS_MONITOR.core_1_montr_ena.core_1_trace_lockup_ena = enable; @@ -184,7 +197,8 @@ FORCE_INLINE_ATTR void assist_debug_ll_lockup_monitor_enable(uint32_t core_id, b // trap_idx: 0 = latest trap, 1 = previous trap // MCause for the exception -FORCE_INLINE_ATTR uint32_t assist_debug_ll_lockup_get_cause(uint32_t core_id, int trap_idx) +__attribute__((always_inline)) +static inline uint32_t assist_debug_ll_lockup_get_cause(uint32_t core_id, int trap_idx) { if (core_id) { return trap_idx ? BUS_MONITOR.core_1_trace_lockup_cause_1.core_1_trace_lockup_recording_cause_1 @@ -195,7 +209,8 @@ FORCE_INLINE_ATTR uint32_t assist_debug_ll_lockup_get_cause(uint32_t core_id, in } } -FORCE_INLINE_ATTR uint32_t assist_debug_ll_lockup_get_tval(uint32_t core_id, int trap_idx) +__attribute__((always_inline)) +static inline uint32_t assist_debug_ll_lockup_get_tval(uint32_t core_id, int trap_idx) { if (core_id) { return trap_idx ? BUS_MONITOR.core_1_trace_lockup_tval_1.core_1_trace_lockup_recording_tval_1 @@ -206,7 +221,8 @@ FORCE_INLINE_ATTR uint32_t assist_debug_ll_lockup_get_tval(uint32_t core_id, int } } -FORCE_INLINE_ATTR uint32_t assist_debug_ll_lockup_get_iaddr(uint32_t core_id, int trap_idx) +__attribute__((always_inline)) +static inline uint32_t assist_debug_ll_lockup_get_iaddr(uint32_t core_id, int trap_idx) { if (core_id) { return trap_idx ? BUS_MONITOR.core_1_trace_lockup_iaddr_1.core_1_trace_lockup_recording_iaddr_1 @@ -217,7 +233,8 @@ FORCE_INLINE_ATTR uint32_t assist_debug_ll_lockup_get_iaddr(uint32_t core_id, in } } -FORCE_INLINE_ATTR uint32_t assist_debug_ll_lockup_get_priv(uint32_t core_id, int trap_idx) +__attribute__((always_inline)) +static inline uint32_t assist_debug_ll_lockup_get_priv(uint32_t core_id, int trap_idx) { if (core_id) { return trap_idx ? BUS_MONITOR.core_1_trace_lockup_priv_1.core_1_trace_lockup_recording_priv_1 @@ -231,7 +248,8 @@ FORCE_INLINE_ATTR uint32_t assist_debug_ll_lockup_get_priv(uint32_t core_id, int /* Enable the hardware lockup reset for the given core via LP_CLKRST. * This controls whether a CPU lockup (exception inside exception handler) triggers * a system reset. Defaults to 0 on S31 so must be explicitly set. */ -FORCE_INLINE_ATTR void assist_debug_ll_lockup_reset_enable(uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_ll_lockup_reset_enable(uint32_t core_id) { if (core_id) { LP_CLKRST.hpcore1_reset_ctrl.hpcore1_lockup_reset_en = 1; diff --git a/components/hal/esp32s31/include/hal/debug_probe_ll.h b/components/esp_hal_debug_assist/esp32s31/include/hal/debug_probe_ll.h similarity index 100% rename from components/hal/esp32s31/include/hal/debug_probe_ll.h rename to components/esp_hal_debug_assist/esp32s31/include/hal/debug_probe_ll.h diff --git a/components/hal/include/hal/assist_debug_hal.h b/components/esp_hal_debug_assist/include/hal/assist_debug_hal.h similarity index 50% rename from components/hal/include/hal/assist_debug_hal.h rename to components/esp_hal_debug_assist/include/hal/assist_debug_hal.h index 6eceee751f7..9ac3e1933ee 100644 --- a/components/hal/include/hal/assist_debug_hal.h +++ b/components/esp_hal_debug_assist/include/hal/assist_debug_hal.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,7 +7,6 @@ #include #include -#include "esp_attr.h" #include "soc/soc_caps.h" #if SOC_ASSIST_DEBUG_SUPPORTED #include "hal/assist_debug_ll.h" @@ -18,37 +17,44 @@ extern "C" { #endif #if SOC_ASSIST_DEBUG_SUPPORTED -FORCE_INLINE_ATTR void assist_debug_hal_sp_int_enable(uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_hal_sp_int_enable(uint32_t core_id) { assist_debug_ll_sp_spill_interrupt_enable(core_id); } -FORCE_INLINE_ATTR void assist_debug_hal_sp_int_disable(uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_hal_sp_int_disable(uint32_t core_id) { assist_debug_ll_sp_spill_interrupt_disable(core_id); } -FORCE_INLINE_ATTR void assist_debug_hal_sp_int_clear(uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_hal_sp_int_clear(uint32_t core_id) { assist_debug_ll_sp_spill_interrupt_clear(core_id); } -FORCE_INLINE_ATTR void assist_debug_hal_sp_mon_enable(uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_hal_sp_mon_enable(uint32_t core_id) { assist_debug_ll_sp_spill_monitor_enable(core_id); } -FORCE_INLINE_ATTR void assist_debug_hal_sp_mon_disable(uint32_t core_id) +__attribute__((always_inline)) +static inline void assist_debug_hal_sp_mon_disable(uint32_t core_id) { assist_debug_ll_sp_spill_monitor_disable(core_id); } -FORCE_INLINE_ATTR uint32_t assist_debug_hal_get_sp_ovf_pc(uint32_t core_id) +__attribute__((always_inline)) +static inline uint32_t assist_debug_hal_get_sp_ovf_pc(uint32_t core_id) { return assist_debug_ll_sp_spill_get_pc(core_id); } -FORCE_INLINE_ATTR void assist_debug_hal_get_sp_bounds(uint32_t core_id, uint32_t *sp_min, uint32_t *sp_max) +__attribute__((always_inline)) +static inline void assist_debug_hal_get_sp_bounds(uint32_t core_id, uint32_t *sp_min, uint32_t *sp_max) { if (sp_min) { *sp_min = assist_debug_ll_sp_spill_get_min(core_id); @@ -58,13 +64,15 @@ FORCE_INLINE_ATTR void assist_debug_hal_get_sp_bounds(uint32_t core_id, uint32_t } } -FORCE_INLINE_ATTR void assist_debug_hal_set_sp_bounds(uint32_t core_id, uint32_t sp_min, uint32_t sp_max) +__attribute__((always_inline)) +static inline void assist_debug_hal_set_sp_bounds(uint32_t core_id, uint32_t sp_min, uint32_t sp_max) { assist_debug_ll_sp_spill_set_min(core_id, sp_min); assist_debug_ll_sp_spill_set_max(core_id, sp_max); } -FORCE_INLINE_ATTR uint32_t assist_debug_hal_is_sp_ovf_fired(uint32_t core_id) +__attribute__((always_inline)) +static inline uint32_t assist_debug_hal_is_sp_ovf_fired(uint32_t core_id) { return assist_debug_ll_sp_spill_is_fired(core_id); } diff --git a/components/hal/include/hal/debug_probe_types.h b/components/esp_hal_debug_assist/include/hal/debug_probe_types.h similarity index 100% rename from components/hal/include/hal/debug_probe_types.h rename to components/esp_hal_debug_assist/include/hal/debug_probe_types.h diff --git a/components/hal/include/hal/riscv_trace_hal.h b/components/esp_hal_debug_assist/include/hal/riscv_trace_hal.h similarity index 100% rename from components/hal/include/hal/riscv_trace_hal.h rename to components/esp_hal_debug_assist/include/hal/riscv_trace_hal.h diff --git a/components/hal/include/hal/riscv_trace_types.h b/components/esp_hal_debug_assist/include/hal/riscv_trace_types.h similarity index 100% rename from components/hal/include/hal/riscv_trace_types.h rename to components/esp_hal_debug_assist/include/hal/riscv_trace_types.h diff --git a/components/hal/riscv_trace_hal.c b/components/esp_hal_debug_assist/riscv_trace_hal.c similarity index 97% rename from components/hal/riscv_trace_hal.c rename to components/esp_hal_debug_assist/riscv_trace_hal.c index 467fb6e5909..453e4a41161 100644 --- a/components/hal/riscv_trace_hal.c +++ b/components/esp_hal_debug_assist/riscv_trace_hal.c @@ -19,7 +19,6 @@ #include #include "esp_rom_sys.h" -#include "esp_private/periph_ctrl.h" #include "soc/soc_caps.h" #include "hal/riscv_trace_hal.h" #include "hal/assert.h" @@ -33,14 +32,8 @@ _Static_assert(RISCV_TRACE_INTR_MEM_FULL == TRACE_MEM_FULL_INTR_ENA, static void riscv_trace_hal_enable_clock_and_reset(int core_id, trace_dev_t *dev) { -#if SOC_CPU_CORES_NUM > 1 - PERIPH_RCC_ATOMIC() -#endif - { - riscv_trace_ll_enable_bus_clock(true); - riscv_trace_ll_reset_register(core_id); - } - + riscv_trace_ll_enable_bus_clock(true); + riscv_trace_ll_reset_register(core_id); riscv_trace_ll_enable_module_clock(dev, true); } diff --git a/components/esp_hw_support/CMakeLists.txt b/components/esp_hw_support/CMakeLists.txt index 4760f2181f4..a83f9c705eb 100644 --- a/components/esp_hw_support/CMakeLists.txt +++ b/components/esp_hw_support/CMakeLists.txt @@ -40,7 +40,7 @@ if(__ULP_BUILD) return() endif() -set(requires esp_hal_gpio esp_hal_usb esp_hal_pmu esp_hal_regi2c esp_hal_uart) +set(requires esp_hal_gpio esp_hal_usb esp_hal_pmu esp_hal_regi2c esp_hal_uart esp_hal_debug_assist) set(priv_requires efuse # only esp_hw_support/adc_share_hw_ctrl.c requires efuse component spi_flash bootloader_support diff --git a/components/esp_riscv_trace/CMakeLists.txt b/components/esp_riscv_trace/CMakeLists.txt index bad315aeea5..c641cb9c7b1 100644 --- a/components/esp_riscv_trace/CMakeLists.txt +++ b/components/esp_riscv_trace/CMakeLists.txt @@ -9,12 +9,15 @@ endif() if(${target} STREQUAL "linux") set(priv_requires "") + set(requires "") else() set(priv_requires esp_mm) + set(requires esp_hal_debug_assist) endif() idf_component_register(SRCS ${srcs} INCLUDE_DIRS ${public_include} PRIV_INCLUDE_DIRS "src" + REQUIRES "${requires}" PRIV_REQUIRES "${priv_requires}" ) diff --git a/components/esp_system/CMakeLists.txt b/components/esp_system/CMakeLists.txt index 5df2ca9d643..ef9c9713f1f 100644 --- a/components/esp_system/CMakeLists.txt +++ b/components/esp_system/CMakeLists.txt @@ -99,11 +99,12 @@ else() idf_component_register(SRCS "${srcs}" INCLUDE_DIRS include PRIV_REQUIRES spi_flash esp_timer esp_mm - esp_hal_mspi esp_hal_wdt esp_hal_uart esp_hal_clock esp_hal_dma - # [refactor-todo] requirements due to init code, - # should be removable once using component init functions - # link-time registration is used. - bootloader_support esp_pm esp_usb_cdc_rom_console + esp_hal_clock esp_hal_mspi esp_hal_wdt esp_hal_debug_assist + esp_hal_uart esp_hal_dma + # [refactor-todo] requirements due to init code, + # should be removable once using component init functions + # link-time registration is used. + bootloader_support esp_pm esp_usb_cdc_rom_console LDFRAGMENTS "linker.lf" "app.lf") add_subdirectory(port) diff --git a/components/esp_system/port/arch/xtensa/trax.c b/components/esp_system/port/arch/xtensa/trax.c index dd1fe62867f..94866e0e54c 100644 --- a/components/esp_system/port/arch/xtensa/trax.c +++ b/components/esp_system/port/arch/xtensa/trax.c @@ -10,7 +10,7 @@ #include "esp_log.h" #include "xt_trax.h" #include "esp_private/trax.h" -#include "hal/trace_ll.h" +#include "hal/xtensa_trace_ll.h" #include "soc/dport_reg.h" #include "soc/tracemem_config.h" #include "sdkconfig.h" diff --git a/components/hal/CMakeLists.txt b/components/hal/CMakeLists.txt index a4fac2dddd5..b7bd8ad5871 100644 --- a/components/hal/CMakeLists.txt +++ b/components/hal/CMakeLists.txt @@ -56,10 +56,6 @@ if(NOT esp_tee_build AND NOT BOOTLOADER_BUILD) if(CONFIG_SOC_MODEM_CLOCK_IS_INDEPENDENT AND CONFIG_SOC_MODEM_CLOCK_SUPPORTED) list(APPEND srcs "${target}/modem_clock_hal.c") endif() - - if(CONFIG_SOC_RISCV_TRACE_SUPPORTED) - list(APPEND srcs "riscv_trace_hal.c") - endif() endif() set(ldfragments linker.lf) diff --git a/components/riscv/CMakeLists.txt b/components/riscv/CMakeLists.txt index 3c93a824cd7..0f9d5da1fae 100644 --- a/components/riscv/CMakeLists.txt +++ b/components/riscv/CMakeLists.txt @@ -18,10 +18,10 @@ endif() # used by ulp/lp_core/lp_core/lp_core_pmp.c and vector.S. if(BOOTLOADER_BUILD) - set(priv_requires soc hal) + set(priv_requires soc hal esp_hal_debug_assist) set(srcs "rv_utils.c") elseif(esp_tee_build) - set(priv_requires soc hal) + set(priv_requires soc hal esp_hal_debug_assist) set(srcs "rv_utils.c") if(CONFIG_SOC_INT_PLIC_SUPPORTED) list(APPEND srcs "interrupt_plic.c") @@ -29,7 +29,7 @@ elseif(esp_tee_build) list(APPEND srcs "interrupt_clic.c") endif() else() - set(priv_requires soc hal) + set(priv_requires soc hal esp_hal_debug_assist) set(srcs "instruction_decode.c" "interrupt.c" diff --git a/tools/test_apps/system/g1_components/CMakeLists.txt b/tools/test_apps/system/g1_components/CMakeLists.txt index e5d86c73386..d652da0b209 100644 --- a/tools/test_apps/system/g1_components/CMakeLists.txt +++ b/tools/test_apps/system/g1_components/CMakeLists.txt @@ -27,6 +27,7 @@ set(esp_hal_components esp_hal_security esp_hal_systimer esp_hal_regi2c + esp_hal_debug_assist ) set(COMPONENTS ${g0_components} ${g1_components} ${esp_hal_components} main)