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Merge branch 'feature/esp32c61_flash_psram_timing_tuning_v6.0' into 'release/v6.0'

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feat(mspi): support 120MHz flash and psram for esp32c61 (v6.0)

See merge request espressif/esp-idf!45886
This commit is contained in:
morris
2026-03-20 13:55:06 +08:00
parent 308feafe23 c7ae253b89
commit 23e199d646
38 changed files with 135 additions and 272 deletions
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components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
+4 -16
View File
@@ -731,22 +731,6 @@ config SOC_SPI_SCT_CONF_BITLEN_MAX
hex
default 0x3FFFA
config SOC_MEMSPI_SRC_FREQ_120M_SUPPORTED
bool
default y
config SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED
bool
default y
config SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED
bool
default y
config SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED
bool
default y
config SOC_SPIRAM_SUPPORTED
bool
default y
@@ -1191,6 +1175,10 @@ config SOC_SPI_MEM_SUPPORT_CACHE_32BIT_ADDR_MAP
bool
default y
config SOC_SPI_MEM_FLASH_SUPPORT_HPM
bool
default y
config SOC_COEX_HW_PTI
bool
default y
components/soc/esp32s3/include/soc/soc_caps.h
+2 -5
View File
@@ -307,11 +307,6 @@
#define SOC_SPI_SCT_BUFFER_NUM_MAX (1 + SOC_SPI_SCT_REG_NUM) //1-word-bitmap + 14-word-regs
#define SOC_SPI_SCT_CONF_BITLEN_MAX 0x3FFFA //18 bits wide reg
#define SOC_MEMSPI_SRC_FREQ_120M_SUPPORTED 1
#define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1
#define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1
#define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1
/*-------------------------- SPIRAM CAPS ----------------------------------------*/
#define SOC_SPIRAM_SUPPORTED 1
#define SOC_SPIRAM_XIP_SUPPORTED 1
@@ -487,6 +482,8 @@
#define SOC_MEMSPI_CORE_CLK_SHARED_WITH_PSRAM (1)
#define SOC_SPI_MEM_SUPPORT_CACHE_32BIT_ADDR_MAP (1)
#define SOC_SPI_MEM_FLASH_SUPPORT_HPM (1) /*!< Support High Performance Mode */
/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/
#define SOC_COEX_HW_PTI (1)