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feat(esp_libc): add riscv zcmp testing on esp32c5
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@@ -17,6 +17,7 @@ from pytest_embedded_idf.utils import idf_parametrize
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('release_esp32', 'esp32'),
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('release_esp32', 'esp32'),
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('release_esp32c2', 'esp32c2'),
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('release_esp32c2', 'esp32c2'),
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('misaligned_mem', 'esp32c3'),
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('misaligned_mem', 'esp32c3'),
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('zcmp', 'esp32c5'),
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],
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],
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indirect=['config', 'target'],
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indirect=['config', 'target'],
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)
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)
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@@ -0,0 +1 @@
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CONFIG_COMPILER_ENABLE_RISCV_ZCMP=y
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