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feat(bootloader): use CPLL/4 as flash default 80M clock source

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wuzhenghui
2026-09-02 19:20:15 +08:00
parent d25d49d307
commit 175cf9a521
3 changed files with 4 additions and 4 deletions
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components/soc/esp32s31/include/soc/clk_tree_defs.h
+1 -1
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@@ -405,7 +405,7 @@ typedef enum {
* @brief Type of FLASH clock source.
*/
typedef enum {
FLASH_CLK_SRC_DEFAULT = SOC_MOD_CLK_BBPLL, /*!< Select SOC_MOD_CLK_BBPLL as FLASH source clock */
FLASH_CLK_SRC_DEFAULT = SOC_MOD_CLK_CPLL, /*!< Select SOC_MOD_CLK_CPLL as FLASH source clock */
FLASH_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select SOC_MOD_CLK_XTAL as FLASH source clock */
FLASH_CLK_SRC_CPLL = SOC_MOD_CLK_CPLL, /*!< Select SOC_MOD_CLK_CPLL as FLASH source clock */
FLASH_CLK_SRC_BBPLL = SOC_MOD_CLK_BBPLL, /*!< Select SOC_MOD_CLK_BBPLL as FLASH source clock */