From 175cf9a521ea2068a897097c8c7beb67e06a317c Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Mon, 3 Aug 2026 20:00:14 +0800 Subject: [PATCH] feat(bootloader): use CPLL/4 as flash default 80M clock source --- .../bootloader_flash/src/bootloader_flash_config_esp32s31.c | 4 ++-- components/esp_hal_mspi/esp32s31/include/hal/mspi_ll.h | 2 +- components/soc/esp32s31/include/soc/clk_tree_defs.h | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s31.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s31.c index f602074bb63..f9ac78c2b1a 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s31.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s31.c @@ -47,9 +47,9 @@ void IRAM_ATTR bootloader_flash_cs_timing_config(void) void IRAM_ATTR bootloader_init_mspi_clock(void) { cache_hal_disable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); - clk_ll_bbpll_enable(); + clk_ll_cpll_enable(); _mspi_timing_ll_set_flash_core_clock(0, 80); - _mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_BBPLL); + _mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_CPLL); cache_hal_enable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); } diff --git a/components/esp_hal_mspi/esp32s31/include/hal/mspi_ll.h b/components/esp_hal_mspi/esp32s31/include/hal/mspi_ll.h index d58f5f8fad5..dabe3a8868f 100644 --- a/components/esp_hal_mspi/esp32s31/include/hal/mspi_ll.h +++ b/components/esp_hal_mspi/esp32s31/include/hal/mspi_ll.h @@ -48,7 +48,7 @@ extern "C" { #define MSPI_LL_PERIPH_NUM 4 #define MSPI_TIMING_LL_MSPI_ID_0 0 #define MSPI_TIMING_LL_MSPI_ID_1 1 -#define MSPI_TIMING_LL_FLASH_CORE_80M_CLK_DIV 6 +#define MSPI_TIMING_LL_FLASH_CORE_80M_CLK_DIV 4 // PSRAM frequency should be constrained by AXI frequency to avoid FIFO underflow. #define MSPI_TIMING_LL_PSRAM_FREQ_AXI_CONSTRAINED 1 diff --git a/components/soc/esp32s31/include/soc/clk_tree_defs.h b/components/soc/esp32s31/include/soc/clk_tree_defs.h index 4504a342eef..6c5119db2fc 100644 --- a/components/soc/esp32s31/include/soc/clk_tree_defs.h +++ b/components/soc/esp32s31/include/soc/clk_tree_defs.h @@ -405,7 +405,7 @@ typedef enum { * @brief Type of FLASH clock source. */ typedef enum { - FLASH_CLK_SRC_DEFAULT = SOC_MOD_CLK_BBPLL, /*!< Select SOC_MOD_CLK_BBPLL as FLASH source clock */ + FLASH_CLK_SRC_DEFAULT = SOC_MOD_CLK_CPLL, /*!< Select SOC_MOD_CLK_CPLL as FLASH source clock */ FLASH_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select SOC_MOD_CLK_XTAL as FLASH source clock */ FLASH_CLK_SRC_CPLL = SOC_MOD_CLK_CPLL, /*!< Select SOC_MOD_CLK_CPLL as FLASH source clock */ FLASH_CLK_SRC_BBPLL = SOC_MOD_CLK_BBPLL, /*!< Select SOC_MOD_CLK_BBPLL as FLASH source clock */