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feat(bootloader): use CPLL/4 as flash default 80M clock source

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wuzhenghui
2026-09-02 19:20:15 +08:00
parent d25d49d307
commit 175cf9a521
3 changed files with 4 additions and 4 deletions
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components/esp_hal_mspi/esp32s31/include/hal/mspi_ll.h
+1 -1
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@@ -48,7 +48,7 @@ extern "C" {
#define MSPI_LL_PERIPH_NUM 4
#define MSPI_TIMING_LL_MSPI_ID_0 0
#define MSPI_TIMING_LL_MSPI_ID_1 1
#define MSPI_TIMING_LL_FLASH_CORE_80M_CLK_DIV 6
#define MSPI_TIMING_LL_FLASH_CORE_80M_CLK_DIV 4
// PSRAM frequency should be constrained by AXI frequency to avoid FIFO underflow.
#define MSPI_TIMING_LL_PSRAM_FREQ_AXI_CONSTRAINED 1