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feat(bootloader): use CPLL/4 as flash default 80M clock source

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wuzhenghui
2026-08-03 20:00:14 +08:00
parent d25d49d307
commit 175cf9a521
3 changed files with 4 additions and 4 deletions
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4
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s31.c
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@@ -47,9 +47,9 @@ void IRAM_ATTR bootloader_flash_cs_timing_config(void)
void IRAM_ATTR bootloader_init_mspi_clock(void)
{
cache_hal_disable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
clk_ll_bbpll_enable();
clk_ll_cpll_enable();
_mspi_timing_ll_set_flash_core_clock(0, 80);
_mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_BBPLL);
_mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_CPLL);
cache_hal_enable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
}