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Merge branch 'feature/esp32p4_eco5_io_hold_v5.4' into 'release/v5.4'

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feat(gpio): add IO hold support for Deep-sleep for ESP32-P4 ECO5 (v5.4)

See merge request espressif/esp-idf!43309
This commit is contained in:
morris
2025-11-19 16:32:25 +08:00
parent 7f11b39856 f322fb55cb
commit 14dd2d23fa
45 changed files with 143 additions and 10311 deletions
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16
components/esp_driver_gpio/include/driver/gpio.h
View File

@@ -385,23 +385,25 @@ esp_err_t gpio_get_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t *stren
* signal or the IO MUX/GPIO configuration is modified (including input enable, output enable, output value,
* function, and drive strength values). This function can be used to retain the state of GPIOs when the power
* domain of where GPIO/IOMUX belongs to becomes off. For example, chip or system is reset (e.g. watchdog
* time-out, deep-sleep events are triggered), or peripheral power-down in light-sleep.
* time-out, Deep-sleep events are triggered), or peripheral power-down in Light-sleep.
*
* This function works in both input and output modes, and only applicable to output-capable GPIOs.
* If this function is enabled:
* in output mode: the output level of the GPIO will be locked and can not be changed.
* in input mode: the input read value can still reflect the changes of the input signal.
*
* Power down or call `gpio_hold_dis` will disable this function.
*
* Please be aware that,
*
* On ESP32P4, the states of IOs can not be hold after waking up from Deep-sleep.
* 1. USB pads cannot hold at low level after waking up from Deep-sleep. The USB related registers are reset, so the USB pull-up is back.
*
* Additionally, on ESP32/S2/C3/S3/C2, this function cannot be used to hold the state of a digital GPIO during Deep-sleep.
* 2. For ESP32-P4 rev < 3.0, the states of IOs can not be hold after waking up from Deep-sleep.
*
* 3. For ESP32/S2/C3/S3/C2, this function cannot be used to hold the state of a digital GPIO during Deep-sleep.
* Even if this function is enabled, the digital GPIO will be reset to its default state when the chip wakes up from
* Deep-sleep. If you want to hold the state of a digital GPIO during Deep-sleep, please call `gpio_deep_sleep_hold_en`.
*
* Power down or call `gpio_hold_dis` will disable this function.
*
* @param gpio_num GPIO number, only support output-capable GPIOs
*
* @return
@@ -429,7 +431,7 @@ esp_err_t gpio_hold_en(gpio_num_t gpio_num);
*/
esp_err_t gpio_hold_dis(gpio_num_t gpio_num);
#if SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
#if !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
/**
* @brief Enable all digital gpio pads hold function during Deep-sleep.
*
@@ -453,7 +455,7 @@ void gpio_deep_sleep_hold_en(void);
* @brief Disable all digital gpio pads hold function during Deep-sleep.
*/
void gpio_deep_sleep_hold_dis(void);
#endif //SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
#endif //!SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
/**
* @brief Set pad input to a peripheral signal through the IOMUX.

6
components/esp_driver_gpio/src/gpio.c
View File

@@ -8,13 +8,13 @@
#include "esp_err.h"
#include "freertos/FreeRTOS.h"
#include "esp_heap_caps.h"
#include "sdkconfig.h"
#include "driver/gpio.h"
#include "driver/rtc_io.h"
#include "soc/interrupts.h"
#if !CONFIG_FREERTOS_UNICORE
#include "esp_ipc.h"
#endif
#include "soc/soc_caps.h"
#include "soc/gpio_periph.h"
#include "esp_log.h"
@@ -755,7 +755,7 @@ esp_err_t gpio_hold_dis(gpio_num_t gpio_num)
return ret;
}
#if SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
#if !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
void gpio_deep_sleep_hold_en(void)
{
portENTER_CRITICAL(&gpio_context.gpio_spinlock);
@@ -769,7 +769,7 @@ void gpio_deep_sleep_hold_dis(void)
gpio_hal_deep_sleep_hold_dis(gpio_context.gpio_hal);
portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
}
#endif //SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
#endif //!SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
#if SOC_GPIO_SUPPORT_FORCE_HOLD
esp_err_t IRAM_ATTR gpio_force_hold_all()

35
components/esp_driver_gpio/test_apps/gpio/main/test_gpio.c
View File

@@ -879,7 +879,7 @@ TEST_CASE("GPIO_light_sleep_wake_up_test", "[gpio][ignore]")
}
#endif
#if SOC_DEEP_SLEEP_SUPPORTED && SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
#if SOC_DEEP_SLEEP_SUPPORTED
// Pick one digital IO for each target to test is enough
static void gpio_deep_sleep_hold_test_first_stage(void)
{
@@ -897,7 +897,9 @@ static void gpio_deep_sleep_hold_test_first_stage(void)
.pull_up_en = 0,
};
TEST_ESP_OK(gpio_config(&io_conf));
TEST_ESP_OK(gpio_set_level(io_num, 0));
const bool initial_level = gpio_get_level(io_num);
TEST_ESP_OK(gpio_set_level(io_num, !initial_level));
// Enable global persistence
TEST_ESP_OK(gpio_hold_en(io_num));
@@ -906,6 +908,10 @@ static void gpio_deep_sleep_hold_test_first_stage(void)
// Extra step is required, so that all digital IOs can automatically get held when entering Deep-sleep
gpio_deep_sleep_hold_en();
#endif
vTaskDelay(pdMS_TO_TICKS(200));
TEST_ESP_OK(gpio_set_level(io_num, initial_level));
TEST_ASSERT_EQUAL_INT(!initial_level, gpio_get_level(io_num));
vTaskDelay(pdMS_TO_TICKS(200));
esp_deep_sleep_start();
}
@@ -916,16 +922,31 @@ static void gpio_deep_sleep_hold_test_second_stage(void)
// Check reset reason is waking up from deepsleep
TEST_ASSERT_EQUAL(ESP_RST_DEEPSLEEP, esp_reset_reason());
// Pin should stay at low level after the deep sleep
TEST_ASSERT_EQUAL_INT(0, gpio_get_level(io_num));
#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3 // DIG-399
bool level = gpio_get_level(io_num);
// Set level should not take effect since hold is still active (and the INPUT_OUTPUT mode should still be held)
TEST_ESP_OK(gpio_set_level(io_num, 1));
TEST_ASSERT_EQUAL_INT(0, gpio_get_level(io_num));
TEST_ESP_OK(gpio_set_level(io_num, !level));
TEST_ASSERT_EQUAL_INT(level, gpio_get_level(io_num));
#endif
#if !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
gpio_deep_sleep_hold_dis();
#endif
TEST_ESP_OK(gpio_hold_dis(io_num));
gpio_config_t io_conf = {
.intr_type = GPIO_INTR_DISABLE,
.mode = GPIO_MODE_INPUT_OUTPUT,
.pin_bit_mask = (1ULL << io_num),
.pull_down_en = GPIO_PULLDOWN_DISABLE,
.pull_up_en = GPIO_PULLUP_DISABLE,
};
TEST_ESP_OK(gpio_config(&io_conf));
#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3 // DIG-399
// Check that the hold level after wakeup is the level before entering deep sleep
TEST_ASSERT_EQUAL_INT(!level, gpio_get_level(io_num));
#endif
}
/*
@@ -937,4 +958,4 @@ static void gpio_deep_sleep_hold_test_second_stage(void)
TEST_CASE_MULTIPLE_STAGES("GPIO_deep_sleep_output_hold_test", "[gpio]",
gpio_deep_sleep_hold_test_first_stage,
gpio_deep_sleep_hold_test_second_stage)
#endif // SOC_DEEP_SLEEP_SUPPORTED && SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
#endif // SOC_DEEP_SLEEP_SUPPORTED

1
components/esp_driver_gpio/test_apps/gpio/main/test_gpio.h
View File

@@ -39,6 +39,7 @@ extern "C" {
#define TEST_GPIO_EXT_IN_IO (3)
#define TEST_GPIO_INPUT_LEVEL_LOW_PIN (1)
#define TEST_GPIO_SIGNAL_IDX (SIG_IN_FUNC250_IDX)
#define TEST_GPIO_DEEP_SLEEP_HOLD_PIN (28)
#elif CONFIG_IDF_TARGET_ESP32H2
#define TEST_GPIO_EXT_OUT_IO (2)
#define TEST_GPIO_EXT_IN_IO (3)

6
components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.c
View File

@@ -235,7 +235,7 @@ TEST_CASE("RTCIO_output_hold_test", "[rtcio]")
#endif //SOC_RTCIO_HOLD_SUPPORTED
#endif //SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
#if SOC_DEEP_SLEEP_SUPPORTED && SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
#if SOC_DEEP_SLEEP_SUPPORTED
// It is not necessary to test every rtcio pin, it will take too much ci testing time for deep sleep
// Only tests on s_test_map[TEST_RTCIO_DEEP_SLEEP_PIN_INDEX] pin
// The default configuration of these pads is low level
@@ -268,8 +268,10 @@ static void rtcio_deep_sleep_hold_test_second_stage(void)
int io_num = s_test_map[TEST_RTCIO_DEEP_SLEEP_PIN_INDEX];
// Check reset reason is waking up from deepsleep
TEST_ASSERT_EQUAL(ESP_RST_DEEPSLEEP, esp_reset_reason());
#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3 // DIG-399
// Pin should stay at high level after the deep sleep
TEST_ASSERT_EQUAL_INT(1, gpio_get_level(io_num));
#endif
gpio_hold_dis(io_num);
}
@@ -283,4 +285,4 @@ static void rtcio_deep_sleep_hold_test_second_stage(void)
TEST_CASE_MULTIPLE_STAGES("RTCIO_deep_sleep_output_hold_test", "[rtcio]",
rtcio_deep_sleep_hold_test_first_stage,
rtcio_deep_sleep_hold_test_second_stage)
#endif // SOC_DEEP_SLEEP_SUPPORTED && SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
#endif // SOC_DEEP_SLEEP_SUPPORTED

1
components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.h
View File

@@ -146,6 +146,7 @@ const int s_test_map[TEST_GPIO_PIN_COUNT] = {
GPIO_NUM_14, //GPIO14
GPIO_NUM_15, //GPIO15
};
#define TEST_RTCIO_DEEP_SLEEP_PIN_INDEX 5 // IO5
#elif CONFIG_IDF_TARGET_ESP32C61
// Has no input-only rtcio pins, all pins support pull-up/down
#define RTCIO_SUPPORT_PU_PD(num) 1

2
components/esp_hw_support/include/esp_private/esp_sleep_internal.h
View File

@@ -74,7 +74,7 @@ esp_err_t esp_sleep_sub_mode_force_disable(esp_sleep_sub_mode_t mode);
*/
int32_t* esp_sleep_sub_mode_dump_config(FILE *stream);
#if SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
#if !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
/**
* @brief Isolate all digital IOs except those that are held during deep sleep
*

15
components/esp_hw_support/port/esp32p4/private_include/pmu_param.h
View File

@@ -11,6 +11,7 @@
#include <esp_types.h>
#include "soc/pmu_struct.h"
#include "hal/pmu_hal.h"
#include "sdkconfig.h"
#ifdef __cplusplus
extern "C" {
@@ -330,6 +331,7 @@ typedef struct {
} pmu_sleep_digital_config_t;
#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3
#define PMU_SLEEP_DIGITAL_DSLP_CONFIG_DEFAULT(sleep_flags) { \
.syscntl = { \
.dig_pad_slp_sel = 0, \
@@ -343,6 +345,19 @@ typedef struct {
.lp_pad_hold_all = (sleep_flags & PMU_SLEEP_PD_LP_PERIPH) ? 1 : 0, \
} \
}
#else // !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
#define PMU_SLEEP_DIGITAL_DSLP_CONFIG_DEFAULT(sleep_flags) { \
.syscntl = { \
.dig_pad_slp_sel = 0, \
} \
}
#define PMU_SLEEP_DIGITAL_LSLP_CONFIG_DEFAULT(sleep_flags) { \
.syscntl = { \
.dig_pad_slp_sel = 0, \
} \
}
#endif
typedef struct {
struct {

4
components/esp_hw_support/sleep_gpio.c
View File

@@ -126,7 +126,7 @@ void esp_sleep_enable_gpio_switch(bool enable)
}
}
#if SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
#if !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
IRAM_ATTR void esp_sleep_isolate_digital_gpio(void)
{
gpio_hal_context_t gpio_hal = {
@@ -164,7 +164,7 @@ IRAM_ATTR void esp_sleep_isolate_digital_gpio(void)
}
}
}
#endif //SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
#endif //!SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
#if SOC_DEEP_SLEEP_SUPPORTED
void esp_deep_sleep_wakeup_io_reset(void)

2
components/esp_hw_support/sleep_modes.c
View File

@@ -987,7 +987,7 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t sleep_flags, esp_sleep_mode_
}
#endif
if (deep_sleep) {
#if SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
#if !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
esp_sleep_isolate_digital_gpio();
#endif

4
components/esp_system/port/CMakeLists.txt
View File

@@ -6,6 +6,10 @@ endif()
target_include_directories(${COMPONENT_LIB} PRIVATE ${INCLUDE_FILES} include/private)
if(CONFIG_ESP32P4_SELECTS_REV_LESS_V3 AND CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_400)
message(WARNING "400 MHz CPU frequency is not guaranteed to work on all chips with revision prior to rev 3!")
endif()
set(srcs "cpu_start.c" "panic_handler.c" "esp_system_chip.c")
if(NOT CONFIG_APP_BUILD_TYPE_PURE_RAM_APP)

26
components/hal/esp32p4/include/hal/gpio_ll.h
View File

@@ -22,6 +22,7 @@
#include "soc/io_mux_reg.h"
#include "soc/io_mux_struct.h"
#include "soc/hp_system_struct.h"
#include "soc/lp_system_struct.h"
#include "soc/lp_iomux_struct.h"
#include "soc/hp_sys_clkrst_struct.h"
#include "soc/pmu_struct.h"
@@ -31,6 +32,7 @@
#include "hal/gpio_types.h"
#include "hal/misc.h"
#include "hal/assert.h"
#include "hal/config.h"
#ifdef __cplusplus
extern "C" {
@@ -504,6 +506,13 @@ static inline void gpio_ll_get_drive_capability(gpio_dev_t *hw, uint32_t gpio_nu
__attribute__((always_inline))
static inline void gpio_ll_hold_en(gpio_dev_t *hw, uint32_t gpio_num)
{
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
if (gpio_num < 32) {
LP_SYS.pad_rtc_hold_ctrl0.pad_rtc_hold_ctrl0 |= (1 << gpio_num);
} else {
LP_SYS.pad_rtc_hold_ctrl1.pad_rtc_hold_ctrl1 |= (1 << (gpio_num - 32));
}
#else
uint64_t bit_mask = 1ULL << gpio_num;
if (!(bit_mask & SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK)) {
// GPIO 0-15
@@ -519,6 +528,7 @@ static inline void gpio_ll_hold_en(gpio_dev_t *hw, uint32_t gpio_num)
HP_SYSTEM.gpio_o_hold_ctrl1.reg_gpio_0_hold_high |= (bit_mask >> (32 + SOC_RTCIO_PIN_COUNT));
}
}
#endif
}
/**
@@ -530,6 +540,13 @@ static inline void gpio_ll_hold_en(gpio_dev_t *hw, uint32_t gpio_num)
__attribute__((always_inline))
static inline void gpio_ll_hold_dis(gpio_dev_t *hw, uint32_t gpio_num)
{
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
if (gpio_num < 32) {
LP_SYS.pad_rtc_hold_ctrl0.pad_rtc_hold_ctrl0 &= ~(1 << gpio_num);
} else {
LP_SYS.pad_rtc_hold_ctrl1.pad_rtc_hold_ctrl1 &= ~(1 << (gpio_num - 32));
}
#else
uint64_t bit_mask = 1ULL << gpio_num;
if (!(bit_mask & SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK)) {
// GPIO 0-15
@@ -545,6 +562,7 @@ static inline void gpio_ll_hold_dis(gpio_dev_t *hw, uint32_t gpio_num)
HP_SYSTEM.gpio_o_hold_ctrl1.reg_gpio_0_hold_high &= ~(bit_mask >> (32 + SOC_RTCIO_PIN_COUNT));
}
}
#endif
}
/**
@@ -567,6 +585,13 @@ static inline bool gpio_ll_is_digital_io_hold(gpio_dev_t *hw, uint32_t gpio_num)
// GPIO 0-15
abort();
} else {
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
if (gpio_num < 32) {
return !!(LP_SYS.pad_rtc_hold_ctrl0.pad_rtc_hold_ctrl0 & (1 << gpio_num));
} else {
return !!(LP_SYS.pad_rtc_hold_ctrl1.pad_rtc_hold_ctrl1 & (1 << (gpio_num - 32)));
}
#else
if (gpio_num < 32 + SOC_RTCIO_PIN_COUNT) {
// GPIO 16-47
return !!(HP_SYSTEM.gpio_o_hold_ctrl0.reg_gpio_0_hold_low & (bit_mask >> SOC_RTCIO_PIN_COUNT));
@@ -574,6 +599,7 @@ static inline bool gpio_ll_is_digital_io_hold(gpio_dev_t *hw, uint32_t gpio_num)
// GPIO 48-54
return !!(HP_SYSTEM.gpio_o_hold_ctrl1.reg_gpio_0_hold_high & (bit_mask >> (32 + SOC_RTCIO_PIN_COUNT)));
}
#endif
}
}

10
components/hal/esp32p4/include/hal/rtc_io_ll.h
View File

@@ -18,9 +18,11 @@
#include "soc/lp_gpio_struct.h"
#include "soc/lp_iomux_struct.h"
#include "soc/lp_gpio_sig_map.h"
#include "soc/lp_system_struct.h"
#include "soc/pmu_struct.h"
#include "hal/misc.h"
#include "hal/assert.h"
#include "hal/config.h"
#ifdef __cplusplus
extern "C" {
@@ -323,9 +325,13 @@ static inline bool rtcio_ll_is_pulldown_enabled(int rtcio_num)
*/
static inline void rtcio_ll_force_hold_enable(int rtcio_num)
{
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
LP_SYS.pad_rtc_hold_ctrl0.pad_rtc_hold_ctrl0 |= BIT(rtcio_num);
#else
uint32_t hold_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_IOMUX.lp_pad_hold, reg_lp_gpio_hold);
hold_mask |= BIT(rtcio_num);
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IOMUX.lp_pad_hold, reg_lp_gpio_hold, hold_mask);
#endif
}
/**
@@ -336,9 +342,13 @@ static inline void rtcio_ll_force_hold_enable(int rtcio_num)
*/
static inline void rtcio_ll_force_hold_disable(int rtcio_num)
{
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
LP_SYS.pad_rtc_hold_ctrl0.pad_rtc_hold_ctrl0 &= ~BIT(rtcio_num);
#else
uint32_t hold_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_IOMUX.lp_pad_hold, reg_lp_gpio_hold);
hold_mask &= ~BIT(rtcio_num);
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IOMUX.lp_pad_hold, reg_lp_gpio_hold, hold_mask);
#endif
}
/**

4
components/hal/include/hal/gpio_hal.h
View File

@@ -334,7 +334,7 @@ void gpio_hal_intr_disable(gpio_hal_context_t *hal, uint32_t gpio_num);
*/
#define gpio_hal_is_digital_io_hold(hal, gpio_num) gpio_ll_is_digital_io_hold((hal)->dev, gpio_num)
#if SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
#if !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
/**
* @brief Enable all digital gpio pad hold function during Deep-sleep.
*
@@ -365,7 +365,7 @@ void gpio_hal_intr_disable(gpio_hal_context_t *hal, uint32_t gpio_num);
* - false deep sleep hold is disabled
*/
#define gpio_hal_deep_sleep_hold_is_en(hal) gpio_ll_deep_sleep_hold_is_en((hal)->dev)
#endif //SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
#endif //!SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
/**
* @brief Set pad input to a peripheral signal through the IOMUX.

4
components/soc/esp32/include/soc/Kconfig.soc_caps.in
View File

@@ -351,10 +351,6 @@ config SOC_GPIO_CLOCKOUT_CHANNEL_NUM
int
default 3
config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
bool
default y
config SOC_I2C_NUM
int
default 2

3
components/soc/esp32/include/soc/soc_caps.h
View File

@@ -193,9 +193,6 @@
#define SOC_GPIO_CLOCKOUT_BY_IO_MUX (1)
#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3)
// RTC_IOs and DIG_IOs can be hold during deep sleep and after waking up
#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1)
/*-------------------------- I2C CAPS ----------------------------------------*/
// ESP32 has 2 I2C
#define SOC_I2C_NUM (2U)

4
components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
View File

@@ -331,10 +331,6 @@ config SOC_GPIO_CLOCKOUT_CHANNEL_NUM
int
default 3
config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
bool
default y
config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
int
default 8

3
components/soc/esp32c2/include/soc/soc_caps.h
View File

@@ -145,9 +145,6 @@
#define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX (1)
#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3)
// "RTC"_IOs and DIG_IOs can be hold during deep sleep and after waking up
#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1)
/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */

4
components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
View File

@@ -427,10 +427,6 @@ config SOC_GPIO_CLOCKOUT_CHANNEL_NUM
int
default 3
config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
bool
default y
config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
int
default 8

3
components/soc/esp32c3/include/soc/soc_caps.h
View File

@@ -184,9 +184,6 @@
#define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX (1)
#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3)
// "RTC"_IOs and DIG_IOs can be hold during deep sleep and after waking up
#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1)
/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */

4
components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
View File

@@ -539,10 +539,6 @@ config SOC_GPIO_SUPPORT_FORCE_HOLD
bool
default y
config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
bool
default y
config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
bool
default y

2
components/soc/esp32c5/include/soc/soc_caps.h
View File

@@ -229,8 +229,6 @@
// Support to force hold all IOs
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
// LP_IOs and DIG_IOs can be hold during deep sleep and after waking up
#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1)
// Support to hold a single digital I/O when the digital domain is powered off
#define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1)

4
components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
View File

@@ -527,10 +527,6 @@ config SOC_GPIO_SUPPORT_FORCE_HOLD
bool
default y
config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
bool
default y
config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
bool
default y

2
components/soc/esp32c6/include/soc/soc_caps.h
View File

@@ -214,8 +214,6 @@
// Support to force hold all IOs
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
// LP_IOs and DIG_IOs can be hold during deep sleep and after waking up
#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1)
// Support to hold a single digital I/O when the digital domain is powered off
#define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1)

4
components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
View File

@@ -359,10 +359,6 @@ config SOC_GPIO_SUPPORT_FORCE_HOLD
bool
default y
config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
bool
default y
config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
bool
default y

2
components/soc/esp32c61/include/soc/soc_caps.h
View File

@@ -192,8 +192,6 @@
// Support to force hold all IOs
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
// "LP"_IOs and DIG_IOs can be hold during deep sleep and after waking up
#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1)
// Support to hold a single digital I/O when the digital domain is powered off
#define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1)

4
components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
View File

@@ -539,10 +539,6 @@ config SOC_GPIO_SUPPORT_FORCE_HOLD
bool
default y
config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
bool
default y
config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
bool
default y

2
components/soc/esp32h2/include/soc/soc_caps.h
View File

@@ -237,8 +237,6 @@
// Support to force hold all IOs
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
// LP_IOs and DIG_IOs can be hold during deep sleep and after waking up
#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1)
// Support to hold a single digital I/O when the digital domain is powered off
#define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1)

8
components/soc/esp32p4/emac_periph.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -13,9 +13,9 @@ const emac_io_info_t emac_io_idx = {
.mii_tx_clk_i_idx = EMAC_TX_CLK_PAD_IN_IDX,
.mii_tx_en_o_idx = EMAC_PHY_TXEN_PAD_OUT_IDX,
.mii_txd0_o_idx = EMAC_PHY_TXD0_PAD_OUT_IDX,
.mii_txd1_o_idx = EMAC_PHY_TXD0_PAD_OUT_IDX,
.mii_txd2_o_idx = EMAC_PHY_TXD0_PAD_OUT_IDX,
.mii_txd3_o_idx = EMAC_PHY_TXD0_PAD_OUT_IDX,
.mii_txd1_o_idx = EMAC_PHY_TXD1_PAD_OUT_IDX,
.mii_txd2_o_idx = EMAC_PHY_TXD2_PAD_OUT_IDX,
.mii_txd3_o_idx = EMAC_PHY_TXD3_PAD_OUT_IDX,
.mii_rx_clk_i_idx = EMAC_RX_CLK_PAD_IN_IDX,
.mii_rx_dv_i_idx = EMAC_PHY_RXDV_PAD_IN_IDX,
.mii_rxd0_i_idx = EMAC_PHY_RXD0_PAD_IN_IDX,

12
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
View File

@@ -703,6 +703,14 @@ config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
hex
default 0x007FFFFFFFFF0000
config SOC_GPIO_SUPPORT_FORCE_HOLD
bool
default y
config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
bool
default y
config SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX
bool
default y
@@ -723,10 +731,6 @@ config SOC_DEBUG_PROBE_MAX_OUTPUT_WIDTH
int
default 16
config SOC_GPIO_SUPPORT_FORCE_HOLD
bool
default y
config SOC_RTCIO_PIN_COUNT
int
default 16

18
components/soc/esp32p4/include/soc/gpio_sig_map.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -196,13 +196,9 @@
#define PWM1_SYNC2_PAD_IN_IDX 100
#define PWM1_CH2_B_PAD_OUT_IDX 100
#define PWM1_F0_PAD_IN_IDX 101
#define ADP_CHRG_PAD_OUT_IDX 101
#define PWM1_F1_PAD_IN_IDX 102
#define ADP_DISCHRG_PAD_OUT_IDX 102
#define PWM1_F2_PAD_IN_IDX 103
#define ADP_PRB_EN_PAD_OUT_IDX 103
#define PWM1_CAP0_PAD_IN_IDX 104
#define ADP_SNS_EN_PAD_OUT_IDX 104
#define PWM1_CAP1_PAD_IN_IDX 105
#define TWAI0_STANDBY_PAD_OUT_IDX 105
#define PWM1_CAP2_PAD_IN_IDX 106
@@ -224,7 +220,6 @@
#define USB_SRP_SESSEND_PAD_IN_IDX 114
#define USB_OTG11_DRVVBUS_PAD_OUT_IDX 114
#define USB_SRP_CHRGVBUS_PAD_OUT_IDX 115
#define OTG_DRVVBUS_PAD_OUT_IDX 116
#define ULPI_CLK_PAD_IN_IDX 117
#define RNG_CHAIN_CLK_PAD_OUT_IDX 117
#define USB_HSPHY_REFCLK_IN_IDX 118
@@ -260,9 +255,7 @@
#define I3C_SLV_SCL_PAD_OUT_IDX 136
#define I3C_SLV_SDA_PAD_IN_IDX 137
#define I3C_SLV_SDA_PAD_OUT_IDX 137
#define ADP_PRB_PAD_IN_IDX 138
#define I3C_MST_SCL_PULLUP_EN_PAD_OUT_IDX 138
#define ADP_SNS_PAD_IN_IDX 139
#define I3C_MST_SDA_PULLUP_EN_PAD_OUT_IDX 139
#define USB_JTAG_TDO_BRIDGE_PAD_IN_IDX 140
#define USB_JTAG_TDI_BRIDGE_PAD_OUT_IDX 140
@@ -458,13 +451,13 @@
#define CORE_GPIO_IN_PAD_IN27_IDX 241
#define CORE_GPIO_OUT_PAD_OUT27_IDX 241
#define CORE_GPIO_IN_PAD_IN28_IDX 242
#define CORE_GPIO_OUT_PAD_OUT28_IDX 242
#define PARLIO_TX_CS_PAD_OUT_IDX 242 // only exists on ESP32P4 Rev. 3.0 and later
#define CORE_GPIO_IN_PAD_IN29_IDX 243
#define CORE_GPIO_OUT_PAD_OUT29_IDX 243
#define EMAC_PTP_PPS_PAD_OUT_IDX 243
#define CORE_GPIO_IN_PAD_IN30_IDX 244
#define CORE_GPIO_OUT_PAD_OUT30_IDX 244
#define ANA_COMP0_OUT_IDX 244
#define CORE_GPIO_IN_PAD_IN31_IDX 245
#define CORE_GPIO_OUT_PAD_OUT31_IDX 245
#define ANA_COMP1_OUT_IDX 245
#define RMT_SIG_PAD_IN0_IDX 246
#define RMT_SIG_PAD_OUT0_IDX 246
#define RMT_SIG_PAD_IN1_IDX 247
@@ -485,4 +478,5 @@
#define SIG_IN_FUNC254_IDX 254
#define SIG_IN_FUNC255_IDX 255
#define SIG_IN_FUNC255_IDX 255
// version date 230403
#define SIG_GPIO_OUT_IDX 256

8
components/soc/esp32p4/include/soc/soc_caps.h
View File

@@ -265,6 +265,11 @@
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_16~GPIO_NUM_54)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x007FFFFFFFFF0000ULL
// Support to force hold all IOs
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
// Support to hold a single digital I/O when the digital domain is powered off
#define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1) // Supported only on ESP32P4 rev >= 3.0 (see DIG-399)
// The Clock Out signal is route to the pin by GPIO matrix
#define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX (1)
#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (2)
@@ -273,9 +278,6 @@
#define SOC_DEBUG_PROBE_NUM_UNIT (1U) // Number of debug probe units
#define SOC_DEBUG_PROBE_MAX_OUTPUT_WIDTH (16) // Maximum width of the debug probe output in each unit
// Support to force hold all IOs
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
/*-------------------------- RTCIO CAPS --------------------------------------*/
#define SOC_RTCIO_PIN_COUNT 16
#define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1 /* This macro indicates that the target has separate RTC IOMUX hardware feature,

772
components/soc/esp32p4/register/hw_ver3/soc/gpio_ext_eco5_struct.h
View File

@@ -1,772 +0,0 @@
/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: SDM Configure Registers */
/** Type of sigmadeltan register
* Duty Cycle Configure Register of SDMn
*/
typedef union {
struct {
/** sdn_in : R/W; bitpos: [7:0]; default: 0;
* This field is used to configure the duty cycle of sigma delta modulation output.
*/
uint32_t sdn_in:8;
/** sdn_prescale : R/W; bitpos: [15:8]; default: 255;
* This field is used to set a divider value to divide APB clock.
*/
uint32_t sdn_prescale:8;
uint32_t reserved_16:16;
};
uint32_t val;
} gpiosd_sigmadeltan_reg_t;
/** Type of sigmadelta_misc register
* MISC Register
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** function_clk_en : R/W; bitpos: [30]; default: 0;
* Clock enable bit of sigma delta modulation.
*/
uint32_t function_clk_en:1;
/** spi_swap : R/W; bitpos: [31]; default: 0;
* Reserved.
*/
uint32_t spi_swap:1;
};
uint32_t val;
} gpiosd_sigmadelta_misc_reg_t;
/** Group: Glitch filter Configure Registers */
/** Type of glitch_filter_chn register
* Glitch Filter Configure Register of Channeln
*/
typedef union {
struct {
/** filter_ch0_en : R/W; bitpos: [0]; default: 0;
* Glitch Filter channel enable bit.
*/
uint32_t filter_ch0_en:1;
/** filter_ch0_input_io_num : R/W; bitpos: [6:1]; default: 0;
* Glitch Filter input io number.
*/
uint32_t filter_ch0_input_io_num:6;
/** filter_ch0_window_thres : R/W; bitpos: [12:7]; default: 0;
* Glitch Filter window threshold.
*/
uint32_t filter_ch0_window_thres:6;
/** filter_ch0_window_width : R/W; bitpos: [18:13]; default: 0;
* Glitch Filter window width.
*/
uint32_t filter_ch0_window_width:6;
uint32_t reserved_19:13;
};
uint32_t val;
} gpiosd_glitch_filter_chn_reg_t;
/** Group: Etm Configure Registers */
/** Type of etm_event_chn_cfg register
* Etm Config register of Channeln
*/
typedef union {
struct {
/** etm_ch0_event_sel : R/W; bitpos: [5:0]; default: 0;
* Etm event channel select gpio.
*/
uint32_t etm_ch0_event_sel:6;
uint32_t reserved_6:1;
/** etm_ch0_event_en : R/W; bitpos: [7]; default: 0;
* Etm event send enable bit.
*/
uint32_t etm_ch0_event_en:1;
uint32_t reserved_8:24;
};
uint32_t val;
} gpiosd_etm_event_chn_cfg_reg_t;
/** Type of etm_task_p0_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio0_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio0_en:1;
/** etm_task_gpio0_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio0_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio1_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio1_en:1;
/** etm_task_gpio1_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio1_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio2_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio2_en:1;
/** etm_task_gpio2_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio2_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio3_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio3_en:1;
/** etm_task_gpio3_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio3_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p0_cfg_reg_t;
/** Type of etm_task_p1_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio4_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio4_en:1;
/** etm_task_gpio4_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio4_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio5_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio5_en:1;
/** etm_task_gpio5_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio5_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio6_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio6_en:1;
/** etm_task_gpio6_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio6_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio7_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio7_en:1;
/** etm_task_gpio7_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio7_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p1_cfg_reg_t;
/** Type of etm_task_p2_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio8_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio8_en:1;
/** etm_task_gpio8_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio8_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio9_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio9_en:1;
/** etm_task_gpio9_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio9_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio10_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio10_en:1;
/** etm_task_gpio10_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio10_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio11_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio11_en:1;
/** etm_task_gpio11_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio11_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p2_cfg_reg_t;
/** Type of etm_task_p3_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio12_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio12_en:1;
/** etm_task_gpio12_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio12_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio13_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio13_en:1;
/** etm_task_gpio13_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio13_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio14_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio14_en:1;
/** etm_task_gpio14_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio14_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio15_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio15_en:1;
/** etm_task_gpio15_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio15_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p3_cfg_reg_t;
/** Type of etm_task_p4_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio16_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio16_en:1;
/** etm_task_gpio16_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio16_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio17_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio17_en:1;
/** etm_task_gpio17_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio17_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio18_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio18_en:1;
/** etm_task_gpio18_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio18_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio19_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio19_en:1;
/** etm_task_gpio19_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio19_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p4_cfg_reg_t;
/** Type of etm_task_p5_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio20_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio20_en:1;
/** etm_task_gpio20_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio20_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio21_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio21_en:1;
/** etm_task_gpio21_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio21_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio22_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio22_en:1;
/** etm_task_gpio22_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio22_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio23_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio23_en:1;
/** etm_task_gpio23_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio23_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p5_cfg_reg_t;
/** Type of etm_task_p6_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio24_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio24_en:1;
/** etm_task_gpio24_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio24_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio25_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio25_en:1;
/** etm_task_gpio25_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio25_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio26_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio26_en:1;
/** etm_task_gpio26_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio26_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio27_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio27_en:1;
/** etm_task_gpio27_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio27_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p6_cfg_reg_t;
/** Type of etm_task_p7_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio28_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio28_en:1;
/** etm_task_gpio28_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio28_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio29_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio29_en:1;
/** etm_task_gpio29_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio29_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio30_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio30_en:1;
/** etm_task_gpio30_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio30_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio31_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio31_en:1;
/** etm_task_gpio31_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio31_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p7_cfg_reg_t;
/** Type of etm_task_p8_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio32_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio32_en:1;
/** etm_task_gpio32_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio32_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio33_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio33_en:1;
/** etm_task_gpio33_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio33_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio34_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio34_en:1;
/** etm_task_gpio34_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio34_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio35_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio35_en:1;
/** etm_task_gpio35_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio35_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p8_cfg_reg_t;
/** Type of etm_task_p9_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio36_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio36_en:1;
/** etm_task_gpio36_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio36_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio37_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio37_en:1;
/** etm_task_gpio37_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio37_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio38_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio38_en:1;
/** etm_task_gpio38_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio38_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio39_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio39_en:1;
/** etm_task_gpio39_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio39_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p9_cfg_reg_t;
/** Type of etm_task_p10_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio40_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio40_en:1;
/** etm_task_gpio40_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio40_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio41_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio41_en:1;
/** etm_task_gpio41_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio41_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio42_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio42_en:1;
/** etm_task_gpio42_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio42_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio43_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio43_en:1;
/** etm_task_gpio43_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio43_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p10_cfg_reg_t;
/** Type of etm_task_p11_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio44_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio44_en:1;
/** etm_task_gpio44_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio44_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio45_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio45_en:1;
/** etm_task_gpio45_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio45_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio46_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio46_en:1;
/** etm_task_gpio46_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio46_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio47_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio47_en:1;
/** etm_task_gpio47_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio47_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p11_cfg_reg_t;
/** Type of etm_task_p12_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio48_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio48_en:1;
/** etm_task_gpio48_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio48_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio49_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio49_en:1;
/** etm_task_gpio49_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio49_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio50_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio50_en:1;
/** etm_task_gpio50_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio50_sel:3;
uint32_t reserved_20:4;
/** etm_task_gpio51_en : R/W; bitpos: [24]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio51_en:1;
/** etm_task_gpio51_sel : R/W; bitpos: [27:25]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio51_sel:3;
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_etm_task_p12_cfg_reg_t;
/** Type of etm_task_p13_cfg register
* Etm Configure Register to decide which GPIO been chosen
*/
typedef union {
struct {
/** etm_task_gpio52_en : R/W; bitpos: [0]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio52_en:1;
/** etm_task_gpio52_sel : R/W; bitpos: [3:1]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio52_sel:3;
uint32_t reserved_4:4;
/** etm_task_gpio53_en : R/W; bitpos: [8]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio53_en:1;
/** etm_task_gpio53_sel : R/W; bitpos: [11:9]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio53_sel:3;
uint32_t reserved_12:4;
/** etm_task_gpio54_en : R/W; bitpos: [16]; default: 0;
* Enable bit of GPIO response etm task.
*/
uint32_t etm_task_gpio54_en:1;
/** etm_task_gpio54_sel : R/W; bitpos: [19:17]; default: 0;
* GPIO choose a etm task channel.
*/
uint32_t etm_task_gpio54_sel:3;
uint32_t reserved_20:12;
};
uint32_t val;
} gpiosd_etm_task_p13_cfg_reg_t;
/** Group: Version Register */
/** Type of version register
* Version Control Register
*/
typedef union {
struct {
/** gpio_sd_date : R/W; bitpos: [27:0]; default: 35663952;
* Version control register.
*/
uint32_t gpio_sd_date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} gpiosd_version_reg_t;
typedef struct {
volatile gpiosd_sigmadeltan_reg_t sigmadeltan[8];
uint32_t reserved_020;
volatile gpiosd_sigmadelta_misc_reg_t sigmadelta_misc;
uint32_t reserved_028[2];
volatile gpiosd_glitch_filter_chn_reg_t glitch_filter_chn[8];
uint32_t reserved_050[4];
volatile gpiosd_etm_event_chn_cfg_reg_t etm_event_chn_cfg[8];
uint32_t reserved_080[8];
volatile gpiosd_etm_task_p0_cfg_reg_t etm_task_p0_cfg;
volatile gpiosd_etm_task_p1_cfg_reg_t etm_task_p1_cfg;
volatile gpiosd_etm_task_p2_cfg_reg_t etm_task_p2_cfg;
volatile gpiosd_etm_task_p3_cfg_reg_t etm_task_p3_cfg;
volatile gpiosd_etm_task_p4_cfg_reg_t etm_task_p4_cfg;
volatile gpiosd_etm_task_p5_cfg_reg_t etm_task_p5_cfg;
volatile gpiosd_etm_task_p6_cfg_reg_t etm_task_p6_cfg;
volatile gpiosd_etm_task_p7_cfg_reg_t etm_task_p7_cfg;
volatile gpiosd_etm_task_p8_cfg_reg_t etm_task_p8_cfg;
volatile gpiosd_etm_task_p9_cfg_reg_t etm_task_p9_cfg;
volatile gpiosd_etm_task_p10_cfg_reg_t etm_task_p10_cfg;
volatile gpiosd_etm_task_p11_cfg_reg_t etm_task_p11_cfg;
volatile gpiosd_etm_task_p12_cfg_reg_t etm_task_p12_cfg;
volatile gpiosd_etm_task_p13_cfg_reg_t etm_task_p13_cfg;
uint32_t reserved_0d8[9];
volatile gpiosd_version_reg_t version;
} gpiosd_dev_t;
extern gpiosd_dev_t GPIO;
#ifndef __cplusplus
_Static_assert(sizeof(gpiosd_dev_t) == 0x100, "Invalid size of gpiosd_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

483
components/soc/esp32p4/register/hw_ver3/soc/gpio_sig_map.h
View File

@@ -1,483 +0,0 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#define SD_CARD_CCLK_2_PAD_OUT_IDX 0
#define SD_CARD_CCMD_2_PAD_IN_IDX 1
#define SD_CARD_CCMD_2_PAD_OUT_IDX 1
#define SD_CARD_CDATA0_2_PAD_IN_IDX 2
#define SD_CARD_CDATA0_2_PAD_OUT_IDX 2
#define SD_CARD_CDATA1_2_PAD_IN_IDX 3
#define SD_CARD_CDATA1_2_PAD_OUT_IDX 3
#define SD_CARD_CDATA2_2_PAD_IN_IDX 4
#define SD_CARD_CDATA2_2_PAD_OUT_IDX 4
#define SD_CARD_CDATA3_2_PAD_IN_IDX 5
#define SD_CARD_CDATA3_2_PAD_OUT_IDX 5
#define SD_CARD_CDATA4_2_PAD_IN_IDX 6
#define SD_CARD_CDATA4_2_PAD_OUT_IDX 6
#define SD_CARD_CDATA5_2_PAD_IN_IDX 7
#define SD_CARD_CDATA5_2_PAD_OUT_IDX 7
#define SD_CARD_CDATA6_2_PAD_IN_IDX 8
#define SD_CARD_CDATA6_2_PAD_OUT_IDX 8
#define SD_CARD_CDATA7_2_PAD_IN_IDX 9
#define SD_CARD_CDATA7_2_PAD_OUT_IDX 9
#define UART0_RXD_PAD_IN_IDX 10
#define UART0_TXD_PAD_OUT_IDX 10
#define UART0_CTS_PAD_IN_IDX 11
#define UART0_RTS_PAD_OUT_IDX 11
#define UART0_DSR_PAD_IN_IDX 12
#define UART0_DTR_PAD_OUT_IDX 12
#define UART1_RXD_PAD_IN_IDX 13
#define UART1_TXD_PAD_OUT_IDX 13
#define UART1_CTS_PAD_IN_IDX 14
#define UART1_RTS_PAD_OUT_IDX 14
#define UART1_DSR_PAD_IN_IDX 15
#define UART1_DTR_PAD_OUT_IDX 15
#define UART2_RXD_PAD_IN_IDX 16
#define UART2_TXD_PAD_OUT_IDX 16
#define UART2_CTS_PAD_IN_IDX 17
#define UART2_RTS_PAD_OUT_IDX 17
#define UART2_DSR_PAD_IN_IDX 18
#define UART2_DTR_PAD_OUT_IDX 18
#define UART3_RXD_PAD_IN_IDX 19
#define UART3_TXD_PAD_OUT_IDX 19
#define UART3_CTS_PAD_IN_IDX 20
#define UART3_RTS_PAD_OUT_IDX 20
#define UART3_DSR_PAD_IN_IDX 21
#define UART3_DTR_PAD_OUT_IDX 21
#define UART4_RXD_PAD_IN_IDX 22
#define UART4_TXD_PAD_OUT_IDX 22
#define UART4_CTS_PAD_IN_IDX 23
#define UART4_RTS_PAD_OUT_IDX 23
#define UART4_DSR_PAD_IN_IDX 24
#define UART4_DTR_PAD_OUT_IDX 24
#define I2S0_O_BCK_PAD_IN_IDX 25
#define I2S0_O_BCK_PAD_OUT_IDX 25
#define I2S0_MCLK_PAD_IN_IDX 26
#define I2S0_MCLK_PAD_OUT_IDX 26
#define I2S0_O_WS_PAD_IN_IDX 27
#define I2S0_O_WS_PAD_OUT_IDX 27
#define I2S0_I_SD_PAD_IN_IDX 28
#define I2S0_O_SD_PAD_OUT_IDX 28
#define I2S0_I_BCK_PAD_IN_IDX 29
#define I2S0_I_BCK_PAD_OUT_IDX 29
#define I2S0_I_WS_PAD_IN_IDX 30
#define I2S0_I_WS_PAD_OUT_IDX 30
#define I2S1_O_BCK_PAD_IN_IDX 31
#define I2S1_O_BCK_PAD_OUT_IDX 31
#define I2S1_MCLK_PAD_IN_IDX 32
#define I2S1_MCLK_PAD_OUT_IDX 32
#define I2S1_O_WS_PAD_IN_IDX 33
#define I2S1_O_WS_PAD_OUT_IDX 33
#define I2S1_I_SD_PAD_IN_IDX 34
#define I2S1_O_SD_PAD_OUT_IDX 34
#define I2S1_I_BCK_PAD_IN_IDX 35
#define I2S1_I_BCK_PAD_OUT_IDX 35
#define I2S1_I_WS_PAD_IN_IDX 36
#define I2S1_I_WS_PAD_OUT_IDX 36
#define I2S2_O_BCK_PAD_IN_IDX 37
#define I2S2_O_BCK_PAD_OUT_IDX 37
#define I2S2_MCLK_PAD_IN_IDX 38
#define I2S2_MCLK_PAD_OUT_IDX 38
#define I2S2_O_WS_PAD_IN_IDX 39
#define I2S2_O_WS_PAD_OUT_IDX 39
#define I2S2_I_SD_PAD_IN_IDX 40
#define I2S2_O_SD_PAD_OUT_IDX 40
#define I2S2_I_BCK_PAD_IN_IDX 41
#define I2S2_I_BCK_PAD_OUT_IDX 41
#define I2S2_I_WS_PAD_IN_IDX 42
#define I2S2_I_WS_PAD_OUT_IDX 42
#define I2S0_I_SD1_PAD_IN_IDX 43
#define I2S0_O_SD1_PAD_OUT_IDX 43
#define I2S0_I_SD2_PAD_IN_IDX 44
#define SPI2_DQS_PAD_OUT_IDX 44
#define I2S0_I_SD3_PAD_IN_IDX 45
#define SPI3_CS2_PAD_OUT_IDX 45
#define SPI3_CS1_PAD_OUT_IDX 46
#define SPI3_CK_PAD_IN_IDX 47
#define SPI3_CK_PAD_OUT_IDX 47
#define SPI3_Q_PAD_IN_IDX 48
#define SPI3_QO_PAD_OUT_IDX 48
#define SPI3_D_PAD_IN_IDX 49
#define SPI3_D_PAD_OUT_IDX 49
#define SPI3_HOLD_PAD_IN_IDX 50
#define SPI3_HOLD_PAD_OUT_IDX 50
#define SPI3_WP_PAD_IN_IDX 51
#define SPI3_WP_PAD_OUT_IDX 51
#define SPI3_CS_PAD_IN_IDX 52
#define SPI3_CS_PAD_OUT_IDX 52
#define SPI2_CK_PAD_IN_IDX 53
#define SPI2_CK_PAD_OUT_IDX 53
#define SPI2_Q_PAD_IN_IDX 54
#define SPI2_Q_PAD_OUT_IDX 54
#define SPI2_D_PAD_IN_IDX 55
#define SPI2_D_PAD_OUT_IDX 55
#define SPI2_HOLD_PAD_IN_IDX 56
#define SPI2_HOLD_PAD_OUT_IDX 56
#define SPI2_WP_PAD_IN_IDX 57
#define SPI2_WP_PAD_OUT_IDX 57
#define SPI2_IO4_PAD_IN_IDX 58
#define SPI2_IO4_PAD_OUT_IDX 58
#define SPI2_IO5_PAD_IN_IDX 59
#define SPI2_IO5_PAD_OUT_IDX 59
#define SPI2_IO6_PAD_IN_IDX 60
#define SPI2_IO6_PAD_OUT_IDX 60
#define SPI2_IO7_PAD_IN_IDX 61
#define SPI2_IO7_PAD_OUT_IDX 61
#define SPI2_CS_PAD_IN_IDX 62
#define SPI2_CS_PAD_OUT_IDX 62
#define PCNT_RST_PAD_IN0_IDX 63
#define SPI2_CS1_PAD_OUT_IDX 63
#define PCNT_RST_PAD_IN1_IDX 64
#define SPI2_CS2_PAD_OUT_IDX 64
#define PCNT_RST_PAD_IN2_IDX 65
#define SPI2_CS3_PAD_OUT_IDX 65
#define PCNT_RST_PAD_IN3_IDX 66
#define SPI2_CS4_PAD_OUT_IDX 66
#define SPI2_CS5_PAD_OUT_IDX 67
#define I2C0_SCL_PAD_IN_IDX 68
#define I2C0_SCL_PAD_OUT_IDX 68
#define I2C0_SDA_PAD_IN_IDX 69
#define I2C0_SDA_PAD_OUT_IDX 69
#define I2C1_SCL_PAD_IN_IDX 70
#define I2C1_SCL_PAD_OUT_IDX 70
#define I2C1_SDA_PAD_IN_IDX 71
#define I2C1_SDA_PAD_OUT_IDX 71
#define GPIO_SD0_OUT_IDX 72
#define GPIO_SD1_OUT_IDX 73
#define UART0_SLP_CLK_PAD_IN_IDX 74
#define GPIO_SD2_OUT_IDX 74
#define UART1_SLP_CLK_PAD_IN_IDX 75
#define GPIO_SD3_OUT_IDX 75
#define UART2_SLP_CLK_PAD_IN_IDX 76
#define GPIO_SD4_OUT_IDX 76
#define UART3_SLP_CLK_PAD_IN_IDX 77
#define GPIO_SD5_OUT_IDX 77
#define UART4_SLP_CLK_PAD_IN_IDX 78
#define GPIO_SD6_OUT_IDX 78
#define GPIO_SD7_OUT_IDX 79
#define TWAI0_RX_PAD_IN_IDX 80
#define TWAI0_TX_PAD_OUT_IDX 80
#define TWAI0_BUS_OFF_ON_PAD_OUT_IDX 81
#define TWAI0_CLKOUT_PAD_OUT_IDX 82
#define TWAI1_RX_PAD_IN_IDX 83
#define TWAI1_TX_PAD_OUT_IDX 83
#define TWAI1_BUS_OFF_ON_PAD_OUT_IDX 84
#define TWAI1_CLKOUT_PAD_OUT_IDX 85
#define TWAI2_RX_PAD_IN_IDX 86
#define TWAI2_TX_PAD_OUT_IDX 86
#define TWAI2_BUS_OFF_ON_PAD_OUT_IDX 87
#define TWAI2_CLKOUT_PAD_OUT_IDX 88
#define PWM0_SYNC0_PAD_IN_IDX 89
#define PWM0_CH0_A_PAD_OUT_IDX 89
#define PWM0_SYNC1_PAD_IN_IDX 90
#define PWM0_CH0_B_PAD_OUT_IDX 90
#define PWM0_SYNC2_PAD_IN_IDX 91
#define PWM0_CH1_A_PAD_OUT_IDX 91
#define PWM0_F0_PAD_IN_IDX 92
#define PWM0_CH1_B_PAD_OUT_IDX 92
#define PWM0_F1_PAD_IN_IDX 93
#define PWM0_CH2_A_PAD_OUT_IDX 93
#define PWM0_F2_PAD_IN_IDX 94
#define PWM0_CH2_B_PAD_OUT_IDX 94
#define PWM0_CAP0_PAD_IN_IDX 95
#define PWM1_CH0_A_PAD_OUT_IDX 95
#define PWM0_CAP1_PAD_IN_IDX 96
#define PWM1_CH0_B_PAD_OUT_IDX 96
#define PWM0_CAP2_PAD_IN_IDX 97
#define PWM1_CH1_A_PAD_OUT_IDX 97
#define PWM1_SYNC0_PAD_IN_IDX 98
#define PWM1_CH1_B_PAD_OUT_IDX 98
#define PWM1_SYNC1_PAD_IN_IDX 99
#define PWM1_CH2_A_PAD_OUT_IDX 99
#define PWM1_SYNC2_PAD_IN_IDX 100
#define PWM1_CH2_B_PAD_OUT_IDX 100
#define PWM1_F0_PAD_IN_IDX 101
#define PWM1_F1_PAD_IN_IDX 102
#define PWM1_F2_PAD_IN_IDX 103
#define PWM1_CAP0_PAD_IN_IDX 104
#define PWM1_CAP1_PAD_IN_IDX 105
#define TWAI0_STANDBY_PAD_OUT_IDX 105
#define PWM1_CAP2_PAD_IN_IDX 106
#define TWAI1_STANDBY_PAD_OUT_IDX 106
#define GMII_MDI_PAD_IN_IDX 107
#define TWAI2_STANDBY_PAD_OUT_IDX 107
#define GMAC_PHY_COL_PAD_IN_IDX 108
#define GMII_MDC_PAD_OUT_IDX 108
#define GMAC_PHY_CRS_PAD_IN_IDX 109
#define GMII_MDO_PAD_OUT_IDX 109
#define USB_OTG11_IDDIG_PAD_IN_IDX 110
#define USB_SRP_DISCHRGVBUS_PAD_OUT_IDX 110
#define USB_OTG11_AVALID_PAD_IN_IDX 111
#define USB_OTG11_IDPULLUP_PAD_OUT_IDX 111
#define USB_SRP_BVALID_PAD_IN_IDX 112
#define USB_OTG11_DPPULLDOWN_PAD_OUT_IDX 112
#define USB_OTG11_VBUSVALID_PAD_IN_IDX 113
#define USB_OTG11_DMPULLDOWN_PAD_OUT_IDX 113
#define USB_SRP_SESSEND_PAD_IN_IDX 114
#define USB_OTG11_DRVVBUS_PAD_OUT_IDX 114
#define USB_SRP_CHRGVBUS_PAD_OUT_IDX 115
#define ULPI_CLK_PAD_IN_IDX 117
#define RNG_CHAIN_CLK_PAD_OUT_IDX 117
#define USB_HSPHY_REFCLK_IN_IDX 118
#define HP_PROBE_TOP_OUT0_IDX 118
#define HP_PROBE_TOP_OUT1_IDX 119
#define HP_PROBE_TOP_OUT2_IDX 120
#define HP_PROBE_TOP_OUT3_IDX 121
#define HP_PROBE_TOP_OUT4_IDX 122
#define HP_PROBE_TOP_OUT5_IDX 123
#define HP_PROBE_TOP_OUT6_IDX 124
#define HP_PROBE_TOP_OUT7_IDX 125
#define SD_CARD_DETECT_N_1_PAD_IN_IDX 126
#define LEDC_LS_SIG_OUT_PAD_OUT0_IDX 126
#define SD_CARD_DETECT_N_2_PAD_IN_IDX 127
#define LEDC_LS_SIG_OUT_PAD_OUT1_IDX 127
#define SD_CARD_INT_N_1_PAD_IN_IDX 128
#define LEDC_LS_SIG_OUT_PAD_OUT2_IDX 128
#define SD_CARD_INT_N_2_PAD_IN_IDX 129
#define LEDC_LS_SIG_OUT_PAD_OUT3_IDX 129
#define SD_CARD_WRITE_PRT_1_PAD_IN_IDX 130
#define LEDC_LS_SIG_OUT_PAD_OUT4_IDX 130
#define SD_CARD_WRITE_PRT_2_PAD_IN_IDX 131
#define LEDC_LS_SIG_OUT_PAD_OUT5_IDX 131
#define SD_DATA_STROBE_1_PAD_IN_IDX 132
#define LEDC_LS_SIG_OUT_PAD_OUT6_IDX 132
#define SD_DATA_STROBE_2_PAD_IN_IDX 133
#define LEDC_LS_SIG_OUT_PAD_OUT7_IDX 133
#define I3C_MST_SCL_PAD_IN_IDX 134
#define I3C_MST_SCL_PAD_OUT_IDX 134
#define I3C_MST_SDA_PAD_IN_IDX 135
#define I3C_MST_SDA_PAD_OUT_IDX 135
#define I3C_SLV_SCL_PAD_IN_IDX 136
#define I3C_SLV_SCL_PAD_OUT_IDX 136
#define I3C_SLV_SDA_PAD_IN_IDX 137
#define I3C_SLV_SDA_PAD_OUT_IDX 137
#define I3C_MST_SCL_PULLUP_EN_PAD_OUT_IDX 138
#define I3C_MST_SDA_PULLUP_EN_PAD_OUT_IDX 139
#define USB_JTAG_TDO_BRIDGE_PAD_IN_IDX 140
#define USB_JTAG_TDI_BRIDGE_PAD_OUT_IDX 140
#define PCNT_SIG_CH0_PAD_IN0_IDX 141
#define USB_JTAG_TMS_BRIDGE_PAD_OUT_IDX 141
#define PCNT_SIG_CH0_PAD_IN1_IDX 142
#define USB_JTAG_TCK_BRIDGE_PAD_OUT_IDX 142
#define PCNT_SIG_CH0_PAD_IN2_IDX 143
#define USB_JTAG_TRST_BRIDGE_PAD_OUT_IDX 143
#define PCNT_SIG_CH0_PAD_IN3_IDX 144
#define LCD_CS_PAD_OUT_IDX 144
#define PCNT_SIG_CH1_PAD_IN0_IDX 145
#define LCD_DC_PAD_OUT_IDX 145
#define PCNT_SIG_CH1_PAD_IN1_IDX 146
#define SD_RST_N_1_PAD_OUT_IDX 146
#define PCNT_SIG_CH1_PAD_IN2_IDX 147
#define SD_RST_N_2_PAD_OUT_IDX 147
#define PCNT_SIG_CH1_PAD_IN3_IDX 148
#define SD_CCMD_OD_PULLUP_EN_N_PAD_OUT_IDX 148
#define PCNT_CTRL_CH0_PAD_IN0_IDX 149
#define LCD_PCLK_PAD_OUT_IDX 149
#define PCNT_CTRL_CH0_PAD_IN1_IDX 150
#define CAM_CLK_PAD_OUT_IDX 150
#define PCNT_CTRL_CH0_PAD_IN2_IDX 151
#define LCD_H_ENABLE_PAD_OUT_IDX 151
#define PCNT_CTRL_CH0_PAD_IN3_IDX 152
#define LCD_H_SYNC_PAD_OUT_IDX 152
#define PCNT_CTRL_CH1_PAD_IN0_IDX 153
#define LCD_V_SYNC_PAD_OUT_IDX 153
#define PCNT_CTRL_CH1_PAD_IN1_IDX 154
#define LCD_DATA_OUT_PAD_OUT0_IDX 154
#define PCNT_CTRL_CH1_PAD_IN2_IDX 155
#define LCD_DATA_OUT_PAD_OUT1_IDX 155
#define PCNT_CTRL_CH1_PAD_IN3_IDX 156
#define LCD_DATA_OUT_PAD_OUT2_IDX 156
#define LCD_DATA_OUT_PAD_OUT3_IDX 157
#define CAM_PCLK_PAD_IN_IDX 158
#define LCD_DATA_OUT_PAD_OUT4_IDX 158
#define CAM_H_ENABLE_PAD_IN_IDX 159
#define LCD_DATA_OUT_PAD_OUT5_IDX 159
#define CAM_H_SYNC_PAD_IN_IDX 160
#define LCD_DATA_OUT_PAD_OUT6_IDX 160
#define CAM_V_SYNC_PAD_IN_IDX 161
#define LCD_DATA_OUT_PAD_OUT7_IDX 161
#define CAM_DATA_IN_PAD_IN0_IDX 162
#define LCD_DATA_OUT_PAD_OUT8_IDX 162
#define CAM_DATA_IN_PAD_IN1_IDX 163
#define LCD_DATA_OUT_PAD_OUT9_IDX 163
#define CAM_DATA_IN_PAD_IN2_IDX 164
#define LCD_DATA_OUT_PAD_OUT10_IDX 164
#define CAM_DATA_IN_PAD_IN3_IDX 165
#define LCD_DATA_OUT_PAD_OUT11_IDX 165
#define CAM_DATA_IN_PAD_IN4_IDX 166
#define LCD_DATA_OUT_PAD_OUT12_IDX 166
#define CAM_DATA_IN_PAD_IN5_IDX 167
#define LCD_DATA_OUT_PAD_OUT13_IDX 167
#define CAM_DATA_IN_PAD_IN6_IDX 168
#define LCD_DATA_OUT_PAD_OUT14_IDX 168
#define CAM_DATA_IN_PAD_IN7_IDX 169
#define LCD_DATA_OUT_PAD_OUT15_IDX 169
#define CAM_DATA_IN_PAD_IN8_IDX 170
#define LCD_DATA_OUT_PAD_OUT16_IDX 170
#define CAM_DATA_IN_PAD_IN9_IDX 171
#define LCD_DATA_OUT_PAD_OUT17_IDX 171
#define CAM_DATA_IN_PAD_IN10_IDX 172
#define LCD_DATA_OUT_PAD_OUT18_IDX 172
#define CAM_DATA_IN_PAD_IN11_IDX 173
#define LCD_DATA_OUT_PAD_OUT19_IDX 173
#define CAM_DATA_IN_PAD_IN12_IDX 174
#define LCD_DATA_OUT_PAD_OUT20_IDX 174
#define CAM_DATA_IN_PAD_IN13_IDX 175
#define LCD_DATA_OUT_PAD_OUT21_IDX 175
#define CAM_DATA_IN_PAD_IN14_IDX 176
#define LCD_DATA_OUT_PAD_OUT22_IDX 176
#define CAM_DATA_IN_PAD_IN15_IDX 177
#define LCD_DATA_OUT_PAD_OUT23_IDX 177
#define GMAC_PHY_RXDV_PAD_IN_IDX 178
#define GMAC_PHY_TXEN_PAD_OUT_IDX 178
#define GMAC_PHY_RXD0_PAD_IN_IDX 179
#define GMAC_PHY_TXD0_PAD_OUT_IDX 179
#define GMAC_PHY_RXD1_PAD_IN_IDX 180
#define GMAC_PHY_TXD1_PAD_OUT_IDX 180
#define GMAC_PHY_RXD2_PAD_IN_IDX 181
#define GMAC_PHY_TXD2_PAD_OUT_IDX 181
#define GMAC_PHY_RXD3_PAD_IN_IDX 182
#define GMAC_PHY_TXD3_PAD_OUT_IDX 182
#define GMAC_PHY_RXER_PAD_IN_IDX 183
#define GMAC_PHY_TXER_PAD_OUT_IDX 183
#define GMAC_RX_CLK_PAD_IN_IDX 184
#define DBG_CH0_CLK_IDX 184
#define GMAC_TX_CLK_PAD_IN_IDX 185
#define DBG_CH1_CLK_IDX 185
#define PARLIO_RX_CLK_PAD_IN_IDX 186
#define PARLIO_RX_CLK_PAD_OUT_IDX 186
#define PARLIO_TX_CLK_PAD_IN_IDX 187
#define PARLIO_TX_CLK_PAD_OUT_IDX 187
#define PARLIO_RX_DATA0_PAD_IN_IDX 188
#define PARLIO_TX_DATA0_PAD_OUT_IDX 188
#define PARLIO_RX_DATA1_PAD_IN_IDX 189
#define PARLIO_TX_DATA1_PAD_OUT_IDX 189
#define PARLIO_RX_DATA2_PAD_IN_IDX 190
#define PARLIO_TX_DATA2_PAD_OUT_IDX 190
#define PARLIO_RX_DATA3_PAD_IN_IDX 191
#define PARLIO_TX_DATA3_PAD_OUT_IDX 191
#define PARLIO_RX_DATA4_PAD_IN_IDX 192
#define PARLIO_TX_DATA4_PAD_OUT_IDX 192
#define PARLIO_RX_DATA5_PAD_IN_IDX 193
#define PARLIO_TX_DATA5_PAD_OUT_IDX 193
#define PARLIO_RX_DATA6_PAD_IN_IDX 194
#define PARLIO_TX_DATA6_PAD_OUT_IDX 194
#define PARLIO_RX_DATA7_PAD_IN_IDX 195
#define PARLIO_TX_DATA7_PAD_OUT_IDX 195
#define PARLIO_RX_DATA8_PAD_IN_IDX 196
#define PARLIO_TX_DATA8_PAD_OUT_IDX 196
#define PARLIO_RX_DATA9_PAD_IN_IDX 197
#define PARLIO_TX_DATA9_PAD_OUT_IDX 197
#define PARLIO_RX_DATA10_PAD_IN_IDX 198
#define PARLIO_TX_DATA10_PAD_OUT_IDX 198
#define PARLIO_RX_DATA11_PAD_IN_IDX 199
#define PARLIO_TX_DATA11_PAD_OUT_IDX 199
#define PARLIO_RX_DATA12_PAD_IN_IDX 200
#define PARLIO_TX_DATA12_PAD_OUT_IDX 200
#define PARLIO_RX_DATA13_PAD_IN_IDX 201
#define PARLIO_TX_DATA13_PAD_OUT_IDX 201
#define PARLIO_RX_DATA14_PAD_IN_IDX 202
#define PARLIO_TX_DATA14_PAD_OUT_IDX 202
#define PARLIO_RX_DATA15_PAD_IN_IDX 203
#define PARLIO_TX_DATA15_PAD_OUT_IDX 203
#define HP_PROBE_TOP_OUT8_IDX 204
#define HP_PROBE_TOP_OUT9_IDX 205
#define HP_PROBE_TOP_OUT10_IDX 206
#define HP_PROBE_TOP_OUT11_IDX 207
#define HP_PROBE_TOP_OUT12_IDX 208
#define HP_PROBE_TOP_OUT13_IDX 209
#define HP_PROBE_TOP_OUT14_IDX 210
#define HP_PROBE_TOP_OUT15_IDX 211
#define CONSTANT0_PAD_OUT_IDX 212
#define CONSTANT1_PAD_OUT_IDX 213
#define CORE_GPIO_IN_PAD_IN0_IDX 214
#define CORE_GPIO_OUT_PAD_OUT0_IDX 214
#define CORE_GPIO_IN_PAD_IN1_IDX 215
#define CORE_GPIO_OUT_PAD_OUT1_IDX 215
#define CORE_GPIO_IN_PAD_IN2_IDX 216
#define CORE_GPIO_OUT_PAD_OUT2_IDX 216
#define CORE_GPIO_IN_PAD_IN3_IDX 217
#define CORE_GPIO_OUT_PAD_OUT3_IDX 217
#define CORE_GPIO_IN_PAD_IN4_IDX 218
#define CORE_GPIO_OUT_PAD_OUT4_IDX 218
#define CORE_GPIO_IN_PAD_IN5_IDX 219
#define CORE_GPIO_OUT_PAD_OUT5_IDX 219
#define CORE_GPIO_IN_PAD_IN6_IDX 220
#define CORE_GPIO_OUT_PAD_OUT6_IDX 220
#define CORE_GPIO_IN_PAD_IN7_IDX 221
#define CORE_GPIO_OUT_PAD_OUT7_IDX 221
#define CORE_GPIO_IN_PAD_IN8_IDX 222
#define CORE_GPIO_OUT_PAD_OUT8_IDX 222
#define CORE_GPIO_IN_PAD_IN9_IDX 223
#define CORE_GPIO_OUT_PAD_OUT9_IDX 223
#define CORE_GPIO_IN_PAD_IN10_IDX 224
#define CORE_GPIO_OUT_PAD_OUT10_IDX 224
#define CORE_GPIO_IN_PAD_IN11_IDX 225
#define CORE_GPIO_OUT_PAD_OUT11_IDX 225
#define CORE_GPIO_IN_PAD_IN12_IDX 226
#define CORE_GPIO_OUT_PAD_OUT12_IDX 226
#define CORE_GPIO_IN_PAD_IN13_IDX 227
#define CORE_GPIO_OUT_PAD_OUT13_IDX 227
#define CORE_GPIO_IN_PAD_IN14_IDX 228
#define CORE_GPIO_OUT_PAD_OUT14_IDX 228
#define CORE_GPIO_IN_PAD_IN15_IDX 229
#define CORE_GPIO_OUT_PAD_OUT15_IDX 229
#define CORE_GPIO_IN_PAD_IN16_IDX 230
#define CORE_GPIO_OUT_PAD_OUT16_IDX 230
#define CORE_GPIO_IN_PAD_IN17_IDX 231
#define CORE_GPIO_OUT_PAD_OUT17_IDX 231
#define CORE_GPIO_IN_PAD_IN18_IDX 232
#define CORE_GPIO_OUT_PAD_OUT18_IDX 232
#define CORE_GPIO_IN_PAD_IN19_IDX 233
#define CORE_GPIO_OUT_PAD_OUT19_IDX 233
#define CORE_GPIO_IN_PAD_IN20_IDX 234
#define CORE_GPIO_OUT_PAD_OUT20_IDX 234
#define CORE_GPIO_IN_PAD_IN21_IDX 235
#define CORE_GPIO_OUT_PAD_OUT21_IDX 235
#define CORE_GPIO_IN_PAD_IN22_IDX 236
#define CORE_GPIO_OUT_PAD_OUT22_IDX 236
#define CORE_GPIO_IN_PAD_IN23_IDX 237
#define CORE_GPIO_OUT_PAD_OUT23_IDX 237
#define CORE_GPIO_IN_PAD_IN24_IDX 238
#define CORE_GPIO_OUT_PAD_OUT24_IDX 238
#define CORE_GPIO_IN_PAD_IN25_IDX 239
#define CORE_GPIO_OUT_PAD_OUT25_IDX 239
#define CORE_GPIO_IN_PAD_IN26_IDX 240
#define CORE_GPIO_OUT_PAD_OUT26_IDX 240
#define CORE_GPIO_IN_PAD_IN27_IDX 241
#define CORE_GPIO_OUT_PAD_OUT27_IDX 241
#define CORE_GPIO_IN_PAD_IN28_IDX 242
#define PARLIO_TX_CS_PAD_OUT_IDX 242
#define CORE_GPIO_IN_PAD_IN29_IDX 243
#define EMAC_PTP_PPS_PAD_OUT_IDX 243
#define CORE_GPIO_IN_PAD_IN30_IDX 244
#define ANA_COMP0_OUT_IDX 244
#define CORE_GPIO_IN_PAD_IN31_IDX 245
#define ANA_COMP1_OUT_IDX 245
#define RMT_SIG_PAD_IN0_IDX 246
#define RMT_SIG_PAD_OUT0_IDX 246
#define RMT_SIG_PAD_IN1_IDX 247
#define RMT_SIG_PAD_OUT1_IDX 247
#define RMT_SIG_PAD_IN2_IDX 248
#define RMT_SIG_PAD_OUT2_IDX 248
#define RMT_SIG_PAD_IN3_IDX 249
#define RMT_SIG_PAD_OUT3_IDX 249
#define SIG_IN_FUNC250_IDX 250
#define SIG_IN_FUNC250_IDX 250
#define SIG_IN_FUNC251_IDX 251
#define SIG_IN_FUNC251_IDX 251
#define SIG_IN_FUNC252_IDX 252
#define SIG_IN_FUNC252_IDX 252
#define SIG_IN_FUNC253_IDX 253
#define SIG_IN_FUNC253_IDX 253
#define SIG_IN_FUNC254_IDX 254
#define SIG_IN_FUNC254_IDX 254
#define SIG_IN_FUNC255_IDX 255
#define SIG_IN_FUNC255_IDX 255
// version date 230403
#define SIG_GPIO_OUT_IDX 256

34
components/soc/esp32p4/register/hw_ver3/soc/hp_system_struct.h
View File

@@ -413,37 +413,6 @@ typedef union {
} hp_crypto_ctrl_reg_t;
/** Group: HP GPIO O HOLD CTRL0 REG */
/** Type of gpio_o_hold_ctrl0 register
* NA
*/
typedef union {
struct {
/** reg_gpio_0_hold_low : R/W; bitpos: [31:0]; default: 0;
* hold control for gpio47~16
*/
uint32_t reg_gpio_0_hold_low:32;
};
uint32_t val;
} hp_gpio_o_hold_ctrl0_reg_t;
/** Group: HP GPIO O HOLD CTRL1 REG */
/** Type of gpio_o_hold_ctrl1 register
* NA
*/
typedef union {
struct {
/** reg_gpio_0_hold_high : R/W; bitpos: [8:0]; default: 0;
* hold control for gpio56~48
*/
uint32_t reg_gpio_0_hold_high:9;
uint32_t reserved_9:23;
};
uint32_t val;
} hp_gpio_o_hold_ctrl1_reg_t;
/** Group: HP SYS RDN ECO CS REG */
/** Type of sys_rdn_eco_cs register
* NA
@@ -2149,8 +2118,7 @@ typedef struct hp_system_dev_t {
volatile hp_cpu_corestalled_st_reg_t cpu_corestalled_st;
uint32_t reserved_068[2];
volatile hp_crypto_ctrl_reg_t crypto_ctrl;
volatile hp_gpio_o_hold_ctrl0_reg_t gpio_o_hold_ctrl0;
volatile hp_gpio_o_hold_ctrl1_reg_t gpio_o_hold_ctrl1;
uint32_t reserved_074[2];
volatile hp_sys_rdn_eco_cs_reg_t sys_rdn_eco_cs;
volatile hp_cache_apb_postw_en_reg_t cache_apb_postw_en;
volatile hp_l2_mem_subsize_reg_t l2_mem_subsize;

5466
components/soc/esp32p4/register/hw_ver3/soc/io_mux_eco5_reg.h
View File

File diff suppressed because it is too large Load Diff

3430
components/soc/esp32p4/register/hw_ver3/soc/io_mux_eco5_struct.h
View File

File diff suppressed because it is too large Load Diff

9
components/soc/esp32p4/register/hw_ver3/soc/io_mux_reg.h
View File

@@ -7,8 +7,6 @@
#pragma once
#include "soc/soc.h"
//TODO: IDF-13419
/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
/* Output enable in sleep mode */
#define SLP_OE (BIT(0))
@@ -357,6 +355,7 @@
#define FUNC_GPIO31_GPIO31 1
#define FUNC_GPIO31_GPIO31_0 0
// Strapping: Diag Group Sel1
#define PERIPHS_IO_MUX_U_PAD_GPIO32 (REG_IO_MUX_BASE + 0x84)
#define FUNC_GPIO32_DBG_PSRAM_DQ4_PAD 4
#define FUNC_GPIO32_EMAC_RMII_CLK_PAD 3
@@ -364,6 +363,7 @@
#define FUNC_GPIO32_GPIO32 1
#define FUNC_GPIO32_GPIO32_0 0
// Strapping: Diag Group Sel0
#define PERIPHS_IO_MUX_U_PAD_GPIO33 (REG_IO_MUX_BASE + 0x88)
#define FUNC_GPIO33_DBG_PSRAM_DQ5_PAD 4
#define FUNC_GPIO33_EMAC_PHY_TXEN_PAD 3
@@ -371,6 +371,7 @@
#define FUNC_GPIO33_GPIO33 1
#define FUNC_GPIO33_GPIO33_0 0
// Strapping: USB2JTAG select: 1->usb2jtag 0-> pad_jtag
#define PERIPHS_IO_MUX_U_PAD_GPIO34 (REG_IO_MUX_BASE + 0x8C)
#define FUNC_GPIO34_DBG_PSRAM_DQ6_PAD 4
#define FUNC_GPIO34_EMAC_PHY_TXD0_PAD 3
@@ -378,6 +379,7 @@
#define FUNC_GPIO34_GPIO34 1
#define FUNC_GPIO34_GPIO34_0 0
// Strapping: Boot Mode select 3
#define PERIPHS_IO_MUX_U_PAD_GPIO35 (REG_IO_MUX_BASE + 0x90)
#define FUNC_GPIO35_DBG_PSRAM_DQ7_PAD 4
#define FUNC_GPIO35_EMAC_PHY_TXD1_PAD 3
@@ -385,6 +387,7 @@
#define FUNC_GPIO35_GPIO35 1
#define FUNC_GPIO35_GPIO35_0 0
// Strapping: Boot Mode select 2
#define PERIPHS_IO_MUX_U_PAD_GPIO36 (REG_IO_MUX_BASE + 0x94)
#define FUNC_GPIO36_DBG_PSRAM_DQS_0_PAD 4
#define FUNC_GPIO36_EMAC_PHY_TXER_PAD 3
@@ -392,11 +395,13 @@
#define FUNC_GPIO36_GPIO36 1
#define FUNC_GPIO36_GPIO36_0 0
// Strapping: Boot Mode select 1
#define PERIPHS_IO_MUX_U_PAD_GPIO37 (REG_IO_MUX_BASE + 0x98)
#define FUNC_GPIO37_SPI2_IO7_PAD 2
#define FUNC_GPIO37_GPIO37 1
#define FUNC_GPIO37_UART0_TXD_PAD 0
// Strapping: Boot Mode select 0
#define PERIPHS_IO_MUX_U_PAD_GPIO38 (REG_IO_MUX_BASE + 0x9C)
#define FUNC_GPIO38_SPI2_DQS_PAD 2
#define FUNC_GPIO38_GPIO38 1

1
components/soc/esp32p4/register/hw_ver3/soc/io_mux_struct.h
View File

@@ -10,7 +10,6 @@
extern "C" {
#endif
//TODO: IDF-13419
/** Type of GPIO register
* IO MUX gpio configuration register
*/

18
components/soc/esp32p4/register/hw_ver3/soc/lp_iomux_struct.h
View File

@@ -114,22 +114,6 @@ typedef union {
} lp_iomux_ext_wakeup0_sel_reg_t;
/** Group: lp_pad_hold */
/** Type of lp_pad_hold register
* Reserved
*/
typedef union {
struct {
/** reg_lp_gpio_hold : R/W; bitpos: [15:0]; default: 0;
* Reserved
*/
uint32_t reg_lp_gpio_hold:16;
uint32_t reserved_16:16;
};
uint32_t val;
} lp_iomux_lp_pad_hold_reg_t;
/** Group: lp_pad_hys */
/** Type of lp_pad_hys register
* Reserved
@@ -151,7 +135,7 @@ typedef struct lp_iomux_dev_t {
volatile lp_iomux_ver_date_reg_t ver_date;
volatile lp_iomux_pad_reg_t pad[16];
volatile lp_iomux_ext_wakeup0_sel_reg_t ext_wakeup0_sel;
volatile lp_iomux_lp_pad_hold_reg_t lp_pad_hold;
uint32_t reserved_04c;
volatile lp_iomux_lp_pad_hys_reg_t lp_pad_hys;
} lp_iomux_dev_t;

4
components/soc/esp32s2/include/soc/Kconfig.soc_caps.in
View File

@@ -407,10 +407,6 @@ config SOC_GPIO_CLOCKOUT_CHANNEL_NUM
int
default 3
config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
bool
default y
config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
int
default 8

3
components/soc/esp32s2/include/soc/soc_caps.h
View File

@@ -182,9 +182,6 @@
#define SOC_GPIO_CLOCKOUT_BY_IO_MUX (1)
#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3)
// RTC_IOs and DIG_IOs can be hold during deep sleep and after waking up
#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1)
/*-------------------------- Dedicated GPIO CAPS ---------------------------------------*/
#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */

4
components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
View File

@@ -507,10 +507,6 @@ config SOC_GPIO_CLOCKOUT_CHANNEL_NUM
int
default 3
config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
bool
default y
config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
int
default 8

3
components/soc/esp32s3/include/soc/soc_caps.h
View File

@@ -197,9 +197,6 @@
#define SOC_GPIO_CLOCKOUT_BY_IO_MUX (1)
#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3)
// RTC_IOs and DIG_IOs can be hold during deep sleep and after waking up
#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1)
/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */

4
tools/test_apps/system/g0_components/CMakeLists.txt
View File

@@ -26,6 +26,10 @@ idf_build_set_property(__BUILD_COMPONENT_DEPGRAPH_ENABLED 1)
project(g0_components)
if(CONFIG_IDF_TARGET_ESP32P4)
idf_build_set_property(C_COMPILE_OPTIONS "-DCONFIG_ESP_REV_MIN_FULL=300" APPEND)
endif()
if(CONFIG_IDF_TARGET_ESP32C2)
# clk_tree hal-driver needs CONFIG_XTAL_FREQ
idf_build_set_property(C_COMPILE_OPTIONS "-DCONFIG_XTAL_FREQ=26" APPEND)