Mirrors/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2026-10-01 18:50:34 +03:00
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'feature/chip764_power_glitch_support_v6.1' into 'release/v6.1'

Browse Source 
feat(s31): bootloader power glitch reset config (v6.1)

See merge request espressif/esp-idf!50545
This commit is contained in:
Jiang Jiang Jian
2026-07-17 10:44:46 +08:00
parent 526285007f 4ab85accea
commit 07c65b3819
5 changed files with 98 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/bootloader_support/src/esp32s31/bootloader_esp32s31.c
+5
View File
@@ -34,6 +34,8 @@
#include "esp_rom_sys.h"
#include "hal/clk_tree_ll.h"
#include "hal/psram_ctrlr_ll.h"
#include "soc/regi2c_bias.h"
#include "hal/regi2c_ctrl.h"
ESP_LOG_ATTR_TAG(TAG, "boot.esp32s31");
@@ -61,6 +63,8 @@ static inline void bootloader_hardware_init(void)
_psram_ctrlr_ll_select_clk_source(PSRAM_CTRLR_LL_MSPI_ID_2, PSRAM_CLK_SRC_XTAL);
_psram_ctrlr_ll_select_clk_source(PSRAM_CTRLR_LL_MSPI_ID_3, PSRAM_CLK_SRC_XTAL);
clk_ll_mpll_disable();
REGI2C_WRITE_MASK(I2C_BIAS, I2C_BIAS_DREG_1P1, 10);
REGI2C_WRITE_MASK(I2C_BIAS, I2C_BIAS_DREG_1P1_PVT, 10);
}
void bootloader_enable_cpu_reset_info(void)
@@ -105,6 +109,7 @@ static inline void bootloader_ana_reset_config(void)
{
//Enable BOD reset
brownout_ll_ana_reset_enable(true);
bootloader_power_glitch_reset_config(true);
}
#if SOC_RTC_WDT_SUPPORTED
components/bootloader_support/src/esp32s31/bootloader_soc.c
+22
View File
@@ -4,7 +4,12 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdbool.h>
#include <assert.h>
#include "soc/soc.h"
#include "soc/lp_analog_peri_reg.h"
#include "soc/pmu_reg.h"
#include "hal/regi2c_ctrl.h"
#include "soc/regi2c_saradc.h"
void bootloader_ana_super_wdt_reset_config(bool enable)
{
@@ -15,3 +20,20 @@ void bootloader_ana_clock_glitch_reset_config(bool enable)
{
(void)enable;
}
void bootloader_power_glitch_reset_config(bool enable)
{
//only detect VDDPST POWER GLITCH
SET_PERI_REG_MASK(PMU_ANA_PERI_PWR_CTRL_REG, PMU_RSTB_PERIF_I2C);
SET_PERI_REG_MASK(PMU_ANA_PERI_PWR_CTRL_REG, PMU_XPD_PERIF_I2C);
REGI2C_WRITE_MASK(I2C_SARADC, POWER_GLITCH_XPD_VDET_PERIF, 0);
REGI2C_WRITE_MASK(I2C_SARADC, POWER_GLITCH_XPD_VDET_PLLBB, 0);
REGI2C_WRITE_MASK(I2C_SARADC, POWER_GLITCH_XPD_VDET_PLL, 0);
REG_SET_FIELD(LP_ANA_FIB_ENABLE_REG, LP_ANA_ANA_FIB_PWR_GLITCH_ENA, 0);
if (enable) {
REG_SET_FIELD(LP_ANA_PG_GLITCH_CNTL_REG, LP_ANA_POWER_GLITCH_RESET_ENA, 0xf);
} else {
REG_SET_FIELD(LP_ANA_PG_GLITCH_CNTL_REG, LP_ANA_POWER_GLITCH_RESET_ENA, 0);
}
}