From 47009c5458fe415b43bdf6595b7c829100ee539e Mon Sep 17 00:00:00 2001 From: hongshuqing Date: Fri, 29 May 2026 11:24:12 +0800 Subject: [PATCH 1/2] fix(vol): update dreg_1p1 and dreg_1p1_pvt in bootloader --- .../src/esp32s31/bootloader_esp32s31.c | 4 +++ .../soc/esp32s31/include/soc/regi2c_bias.h | 35 +++++++++++++++++++ 2 files changed, 39 insertions(+) create mode 100644 components/soc/esp32s31/include/soc/regi2c_bias.h diff --git a/components/bootloader_support/src/esp32s31/bootloader_esp32s31.c b/components/bootloader_support/src/esp32s31/bootloader_esp32s31.c index d90ccb52bb5..7e9ccb2eb38 100644 --- a/components/bootloader_support/src/esp32s31/bootloader_esp32s31.c +++ b/components/bootloader_support/src/esp32s31/bootloader_esp32s31.c @@ -34,6 +34,8 @@ #include "esp_rom_sys.h" #include "hal/clk_tree_ll.h" #include "hal/psram_ctrlr_ll.h" +#include "soc/regi2c_bias.h" +#include "hal/regi2c_ctrl.h" ESP_LOG_ATTR_TAG(TAG, "boot.esp32s31"); @@ -61,6 +63,8 @@ static inline void bootloader_hardware_init(void) _psram_ctrlr_ll_select_clk_source(PSRAM_CTRLR_LL_MSPI_ID_2, PSRAM_CLK_SRC_XTAL); _psram_ctrlr_ll_select_clk_source(PSRAM_CTRLR_LL_MSPI_ID_3, PSRAM_CLK_SRC_XTAL); clk_ll_mpll_disable(); + REGI2C_WRITE_MASK(I2C_BIAS, I2C_BIAS_DREG_1P1, 10); + REGI2C_WRITE_MASK(I2C_BIAS, I2C_BIAS_DREG_1P1_PVT, 10); } void bootloader_enable_cpu_reset_info(void) diff --git a/components/soc/esp32s31/include/soc/regi2c_bias.h b/components/soc/esp32s31/include/soc/regi2c_bias.h new file mode 100644 index 00000000000..cd6147635ea --- /dev/null +++ b/components/soc/esp32s31/include/soc/regi2c_bias.h @@ -0,0 +1,35 @@ +/* + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 OR MIT + */ + +#pragma once + +/** + * @file regi2c_bias.h + * @brief Register definitions for bias + * + * This file lists register fields of BIAS. These definitions are used via macros defined in regi2c_ctrl.h, by + * rtc_clk_init function in esp32s31/rtc_clk_init.c. + */ + +#define I2C_BIAS 0x6A +#define I2C_BIAS_HOSTID 0 + +#define I2C_BIAS_DREG_1P6 0 +#define I2C_BIAS_DREG_1P6_MSB 3 +#define I2C_BIAS_DREG_1P6_LSB 0 + +#define I2C_BIAS_DREG_1P1 0 +#define I2C_BIAS_DREG_1P1_MSB 7 +#define I2C_BIAS_DREG_1P1_LSB 4 + +#define I2C_BIAS_DREG_1P1_PVT 1 +#define I2C_BIAS_DREG_1P1_PVT_MSB 3 +#define I2C_BIAS_DREG_1P1_PVT_LSB 0 + +#define I2C_BIAS_DREG_2P2_PVT 1 +#define I2C_BIAS_DREG_2P2_PVT_MSB 7 +#define I2C_BIAS_DREG_2P2_PVT_LSB 4 + From 4ab85acceacd793aa3a70e0b25ad1c03fc444143 Mon Sep 17 00:00:00 2001 From: hongshuqing Date: Fri, 29 May 2026 15:04:17 +0800 Subject: [PATCH 2/2] feat(pwr_glitch): chip764 power glitch reset config --- .../src/esp32s31/bootloader_esp32s31.c | 1 + .../src/esp32s31/bootloader_soc.c | 22 +++++++++++++ .../soc/esp32s31/include/soc/regi2c_bias.h | 1 - .../soc/esp32s31/include/soc/regi2c_saradc.h | 32 +++++++++++++++++++ .../register/soc/lp_analog_peri_reg.h | 5 +++ 5 files changed, 60 insertions(+), 1 deletion(-) diff --git a/components/bootloader_support/src/esp32s31/bootloader_esp32s31.c b/components/bootloader_support/src/esp32s31/bootloader_esp32s31.c index 7e9ccb2eb38..e695019dcbe 100644 --- a/components/bootloader_support/src/esp32s31/bootloader_esp32s31.c +++ b/components/bootloader_support/src/esp32s31/bootloader_esp32s31.c @@ -109,6 +109,7 @@ static inline void bootloader_ana_reset_config(void) { //Enable BOD reset brownout_ll_ana_reset_enable(true); + bootloader_power_glitch_reset_config(true); } #if SOC_RTC_WDT_SUPPORTED diff --git a/components/bootloader_support/src/esp32s31/bootloader_soc.c b/components/bootloader_support/src/esp32s31/bootloader_soc.c index 217af9f97d2..0aac81cc6aa 100644 --- a/components/bootloader_support/src/esp32s31/bootloader_soc.c +++ b/components/bootloader_support/src/esp32s31/bootloader_soc.c @@ -4,7 +4,12 @@ * SPDX-License-Identifier: Apache-2.0 */ #include +#include +#include "soc/soc.h" #include "soc/lp_analog_peri_reg.h" +#include "soc/pmu_reg.h" +#include "hal/regi2c_ctrl.h" +#include "soc/regi2c_saradc.h" void bootloader_ana_super_wdt_reset_config(bool enable) { @@ -15,3 +20,20 @@ void bootloader_ana_clock_glitch_reset_config(bool enable) { (void)enable; } + +void bootloader_power_glitch_reset_config(bool enable) +{ + //only detect VDDPST POWER GLITCH + SET_PERI_REG_MASK(PMU_ANA_PERI_PWR_CTRL_REG, PMU_RSTB_PERIF_I2C); + SET_PERI_REG_MASK(PMU_ANA_PERI_PWR_CTRL_REG, PMU_XPD_PERIF_I2C); + REGI2C_WRITE_MASK(I2C_SARADC, POWER_GLITCH_XPD_VDET_PERIF, 0); + REGI2C_WRITE_MASK(I2C_SARADC, POWER_GLITCH_XPD_VDET_PLLBB, 0); + REGI2C_WRITE_MASK(I2C_SARADC, POWER_GLITCH_XPD_VDET_PLL, 0); + + REG_SET_FIELD(LP_ANA_FIB_ENABLE_REG, LP_ANA_ANA_FIB_PWR_GLITCH_ENA, 0); + if (enable) { + REG_SET_FIELD(LP_ANA_PG_GLITCH_CNTL_REG, LP_ANA_POWER_GLITCH_RESET_ENA, 0xf); + } else { + REG_SET_FIELD(LP_ANA_PG_GLITCH_CNTL_REG, LP_ANA_POWER_GLITCH_RESET_ENA, 0); + } +} diff --git a/components/soc/esp32s31/include/soc/regi2c_bias.h b/components/soc/esp32s31/include/soc/regi2c_bias.h index cd6147635ea..c9e38fe3cd7 100644 --- a/components/soc/esp32s31/include/soc/regi2c_bias.h +++ b/components/soc/esp32s31/include/soc/regi2c_bias.h @@ -32,4 +32,3 @@ #define I2C_BIAS_DREG_2P2_PVT 1 #define I2C_BIAS_DREG_2P2_PVT_MSB 7 #define I2C_BIAS_DREG_2P2_PVT_LSB 4 - diff --git a/components/soc/esp32s31/include/soc/regi2c_saradc.h b/components/soc/esp32s31/include/soc/regi2c_saradc.h index a6602637ff6..6b4af2d10c4 100644 --- a/components/soc/esp32s31/include/soc/regi2c_saradc.h +++ b/components/soc/esp32s31/include/soc/regi2c_saradc.h @@ -62,6 +62,38 @@ #define ADC_SARADC_ENT_TSENS_ADDR_MSB 0x2 #define ADC_SARADC_ENT_TSENS_ADDR_LSB 0x2 +#define POWER_GLITCH_XPD_VDET_PERIF 10 +#define POWER_GLITCH_XPD_VDET_PERIF_MSB 0 +#define POWER_GLITCH_XPD_VDET_PERIF_LSB 0 + +#define POWER_GLITCH_XPD_VDET_VDDPST 10 +#define POWER_GLITCH_XPD_VDET_VDDPST_MSB 1 +#define POWER_GLITCH_XPD_VDET_VDDPST_LSB 1 + +#define POWER_GLITCH_XPD_VDET_PLLBB 10 +#define POWER_GLITCH_XPD_VDET_PLLBB_MSB 2 +#define POWER_GLITCH_XPD_VDET_PLLBB_LSB 2 + +#define POWER_GLITCH_XPD_VDET_PLL 10 +#define POWER_GLITCH_XPD_VDET_PLL_MSB 3 +#define POWER_GLITCH_XPD_VDET_PLL_LSB 3 + +#define POWER_GLITCH_MODE_VDET_PERIF 10 +#define POWER_GLITCH_MODE_VDET_PERIF_MSB 4 +#define POWER_GLITCH_MODE_VDET_PERIF_LSB 4 + +#define POWER_GLITCH_MODE_VDET_VDDPST 10 +#define POWER_GLITCH_MODE_VDET_VDDPST_MSB 5 +#define POWER_GLITCH_MODE_VDET_VDDPST_LSB 5 + +#define POWER_GLITCH_MODE_VDET_PLLBB 10 +#define POWER_GLITCH_MODE_VDET_PLLBB_MSB 6 +#define POWER_GLITCH_MODE_VDET_PLLBB_LSB 6 + +#define POWER_GLITCH_MODE_VDET_PLL 10 +#define POWER_GLITCH_MODE_VDET_PLL_MSB 7 +#define POWER_GLITCH_MODE_VDET_PLL_LSB 7 + #define POWER_GLITCH_DREF_VDET_PERIF 11 #define POWER_GLITCH_DREF_VDET_PERIF_MSB 2 #define POWER_GLITCH_DREF_VDET_PERIF_LSB 0 diff --git a/components/soc/esp32s31/register/soc/lp_analog_peri_reg.h b/components/soc/esp32s31/register/soc/lp_analog_peri_reg.h index 3cc70534cb9..41dd2002445 100644 --- a/components/soc/esp32s31/register/soc/lp_analog_peri_reg.h +++ b/components/soc/esp32s31/register/soc/lp_analog_peri_reg.h @@ -119,6 +119,11 @@ extern "C" { #define LP_ANA_ANA_FIB_ENA_V 0xFFFFFFFFU #define LP_ANA_ANA_FIB_ENA_S 0 +#define LP_ANA_ANA_FIB_PWR_GLITCH_ENA 0x0000000FU +#define LP_ANA_ANA_FIB_PWR_GLITCH_ENA_M (LP_ANA_ANA_FIB_PWR_GLITCH_ENA_V << LP_ANA_ANA_FIB_PWR_GLITCH_ENA_S) +#define LP_ANA_ANA_FIB_PWR_GLITCH_ENA_V 0x0000000FU +#define LP_ANA_ANA_FIB_PWR_GLITCH_ENA_S 2 + /** LP_ANA_INT_RAW_REG register * need_des */