Merge branch 'bugfix/fix_some_external_coex_issues' into 'master'

Bugfix/fix some external coex issues

See merge request espressif/esp-idf!49259
This commit is contained in:
Jiang Jiang Jian
2026-06-24 17:45:52 +08:00
24 changed files with 10 additions and 62 deletions

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@@ -2,5 +2,5 @@
components/esp_coex/test_apps/:
disable:
- if: IDF_TARGET not in ["esp32s2", "esp32s3", "esp32c3", "esp32c2", "esp32c6", "esp32h2", "esp32c5", "esp32c61", "esp32s31"]
reason: only supported with s2, s3, c3, c2, c6, h2, c5, c61 and s31
- if: IDF_TARGET not in ["esp32s2", "esp32s3", "esp32c3", "esp32c2", "esp32c6", "esp32h2", "esp32c5", "esp32c61", "esp32s31", "esp32h4", "esp32h21"]
reason: only supported with s2, s3, c3, c2, c6, h2, c5, c61, s31, esp32h4 and esp32h21

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@@ -1,3 +1,3 @@
| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S2 | ESP32-S3 | ESP32-S31 |
| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | --------- |
| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-S2 | ESP32-S3 | ESP32-S31 |
| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | --------- |

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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Unlicense OR CC0-1.0
*/
@@ -36,12 +36,15 @@ TEST_CASE("enable external coex", "[external_coex]")
#elif CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32C61
#define EXTERNAL_COEX_CONF 0x600AF4A0
#define WDEV_RW_BT_COEX_EN (BIT(9))
#elif CONFIG_IDF_TARGET_ESP32H2
#elif CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32H21
#define EXTERNAL_COEX_CONF 0x600AD4A0
#define WDEV_RW_BT_COEX_EN (BIT(9))
#elif CONFIG_IDF_TARGET_ESP32S31
#define EXTERNAL_COEX_CONF 0x2010F4A0
#define WDEV_RW_BT_COEX_EN (BIT(9))
#elif CONFIG_IDF_TARGET_ESP32H4
#define EXTERNAL_COEX_CONF 0x600CF4A0
#define WDEV_RW_BT_COEX_EN (BIT(9))
#endif
esp_extern_coex_work_mode_t mode = EXTERNAL_COEX_LEADER_ROLE;

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@@ -8,7 +8,7 @@ from pytest_embedded_idf.utils import idf_parametrize
@pytest.mark.generic
@idf_parametrize(
'target',
['esp32h2', 'esp32c3', 'esp32s2', 'esp32s3', 'esp32c6', 'esp32c61', 'esp32c5', 'esp32s31'],
['esp32h2', 'esp32c3', 'esp32s2', 'esp32s3', 'esp32c6', 'esp32c61', 'esp32c5', 'esp32s31', 'esp32h4', 'esp32h21'],
indirect=['target'],
)
def test_external_coex_unit_test(dut: Dut) -> None:

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@@ -571,10 +571,6 @@ config SOC_EXTERNAL_COEX_ADVANCE
bool
default y
config SOC_EXTERNAL_COEX_LEADER_TX_LINE
bool
default n
config SOC_PHY_DIG_REGS_MEM_SIZE
int
default 21

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@@ -263,7 +263,6 @@
/*-------------------------- EXTERNAL COEXISTENCE CAPS -------------------------------------*/
#define SOC_EXTERNAL_COEX_ADVANCE (1) /*!< HARDWARE ADVANCED EXTERNAL COEXISTENCE CAPS */
#define SOC_EXTERNAL_COEX_LEADER_TX_LINE (0) /*!< EXTERNAL COEXISTENCE TX LINE CAPS */
/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/
#define SOC_PHY_DIG_REGS_MEM_SIZE (21*4)

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@@ -783,14 +783,6 @@ config SOC_COEX_HW_PTI
bool
default y
config SOC_EXTERNAL_COEX_ADVANCE
bool
default n
config SOC_EXTERNAL_COEX_LEADER_TX_LINE
bool
default n
config SOC_PHY_DIG_REGS_MEM_SIZE
int
default 21

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@@ -349,8 +349,6 @@
#define SOC_COEX_HW_PTI (1)
/*-------------------------- EXTERNAL COEXISTENCE CAPS -------------------------------------*/
#define SOC_EXTERNAL_COEX_ADVANCE (0) /*!< HARDWARE ADVANCED EXTERNAL COEXISTENCE CAPS */
#define SOC_EXTERNAL_COEX_LEADER_TX_LINE (0) /*!< EXTERNAL COEXISTENCE TX LINE CAPS */
/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/
#define SOC_PHY_DIG_REGS_MEM_SIZE (21*4)

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@@ -1303,10 +1303,6 @@ config SOC_EXTERNAL_COEX_ADVANCE
bool
default y
config SOC_EXTERNAL_COEX_LEADER_TX_LINE
bool
default n
config SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH
int
default 12

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@@ -527,7 +527,6 @@
/*-------------------------- EXTERNAL COEXISTENCE CAPS -------------------------------------*/
#define SOC_EXTERNAL_COEX_ADVANCE (1) /*!< HARDWARE EXTERNAL COEXISTENCE CAPS */
#define SOC_EXTERNAL_COEX_LEADER_TX_LINE (0) /*!< EXTERNAL COEXISTENCE TX LINE CAPS */
/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/
// #define SOC_PHY_DIG_REGS_MEM_SIZE (21*4)

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@@ -1043,10 +1043,6 @@ config SOC_EXTERNAL_COEX_ADVANCE
bool
default y
config SOC_EXTERNAL_COEX_LEADER_TX_LINE
bool
default n
config SOC_PHY_DIG_REGS_MEM_SIZE
int
default 21

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@@ -430,7 +430,6 @@
/*-------------------------- EXTERNAL COEXISTENCE CAPS -------------------------------------*/
#define SOC_EXTERNAL_COEX_ADVANCE (1) /*!< HARDWARE ADVANCED EXTERNAL COEXISTENCE CAPS */
#define SOC_EXTERNAL_COEX_LEADER_TX_LINE (0) /*!< EXTERNAL COEXISTENCE TX LINE CAPS */
/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/
#define SOC_PHY_DIG_REGS_MEM_SIZE (21*4)

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@@ -959,10 +959,6 @@ config SOC_EXTERNAL_COEX_ADVANCE
bool
default y
config SOC_EXTERNAL_COEX_LEADER_TX_LINE
bool
default n
config SOC_PHY_DIG_REGS_MEM_SIZE
int
default 21

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@@ -401,7 +401,6 @@
/*-------------------------- EXTERNAL COEXISTENCE CAPS -------------------------------------*/
#define SOC_EXTERNAL_COEX_ADVANCE (1) /*!< HARDWARE ADVANCED EXTERNAL COEXISTENCE CAPS */
#define SOC_EXTERNAL_COEX_LEADER_TX_LINE (0) /*!< EXTERNAL COEXISTENCE TX LINE CAPS */
/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/
#define SOC_PHY_DIG_REGS_MEM_SIZE (21*4)

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@@ -1051,10 +1051,6 @@ config SOC_EXTERNAL_COEX_ADVANCE
bool
default y
config SOC_EXTERNAL_COEX_LEADER_TX_LINE
bool
default n
config SOC_PHY_DIG_REGS_MEM_SIZE
int
default 21

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@@ -458,7 +458,6 @@
/*-------------------------- EXTERNAL COEXISTENCE CAPS -------------------------------------*/
#define SOC_EXTERNAL_COEX_ADVANCE (1) /*!< HARDWARE ADVANCED EXTERNAL COEXISTENCE CAPS */
#define SOC_EXTERNAL_COEX_LEADER_TX_LINE (0) /*!< EXTERNAL COEXISTENCE TX LINE CAPS */
/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/
#define SOC_PHY_DIG_REGS_MEM_SIZE (21*4)

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@@ -963,10 +963,6 @@ config SOC_EXTERNAL_COEX_ADVANCE
bool
default y
config SOC_EXTERNAL_COEX_LEADER_TX_LINE
bool
default n
config SOC_PHY_DIG_REGS_MEM_SIZE
int
default 21

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@@ -433,7 +433,6 @@
/*-------------------------- EXTERNAL COEXISTENCE CAPS -------------------------------------*/
#define SOC_EXTERNAL_COEX_ADVANCE (1) /*!< HARDWARE ADVANCED EXTERNAL COEXISTENCE CAPS */
#define SOC_EXTERNAL_COEX_LEADER_TX_LINE (0) /*!< EXTERNAL COEXISTENCE TX LINE CAPS */
/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/
#define SOC_PHY_DIG_REGS_MEM_SIZE (21*4)

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@@ -1103,10 +1103,6 @@ config SOC_EXTERNAL_COEX_ADVANCE
bool
default y
config SOC_EXTERNAL_COEX_LEADER_TX_LINE
bool
default n
config SOC_PHY_DIG_REGS_MEM_SIZE
int
default 21

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@@ -467,7 +467,6 @@
/*-------------------------- EXTERNAL COEXISTENCE CAPS -------------------------------------*/
#define SOC_EXTERNAL_COEX_ADVANCE (1) /*!< HARDWARE ADVANCED EXTERNAL COEXISTENCE CAPS */
#define SOC_EXTERNAL_COEX_LEADER_TX_LINE (0) /*!< EXTERNAL COEXISTENCE TX LINE CAPS */
/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/
#define SOC_PHY_DIG_REGS_MEM_SIZE (21*4)

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@@ -959,10 +959,6 @@ config SOC_COEX_HW_PTI
bool
default y
config SOC_EXTERNAL_COEX_ADVANCE
bool
default n
config SOC_EXTERNAL_COEX_LEADER_TX_LINE
bool
default y

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@@ -430,7 +430,6 @@
// No contents
/*-------------------------- EXTERNAL COEXISTENCE CAPS -------------------------------------*/
#define SOC_EXTERNAL_COEX_ADVANCE (0) /*!< HARDWARE ADVANCED EXTERNAL COEXISTENCE CAPS */
#define SOC_EXTERNAL_COEX_LEADER_TX_LINE (1) /*!< EXTERNAL COEXISTENCE TX LINE CAPS */
/*-------------------------- Temperature Sensor CAPS -------------------------------------*/

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@@ -1119,10 +1119,6 @@ config SOC_COEX_HW_PTI
bool
default y
config SOC_EXTERNAL_COEX_ADVANCE
bool
default n
config SOC_EXTERNAL_COEX_LEADER_TX_LINE
bool
default y

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@@ -461,7 +461,6 @@
#define SOC_COEX_HW_PTI (1)
/*-------------------------- EXTERNAL COEXISTENCE CAPS -------------------------------------*/
#define SOC_EXTERNAL_COEX_ADVANCE (0) /*!< HARDWARE ADVANCED EXTERNAL COEXISTENCE CAPS */
#define SOC_EXTERNAL_COEX_LEADER_TX_LINE (1) /*!< EXTERNAL COEXISTENCE TX LINE CAPS */
/*-------------------------- SDMMC CAPS -----------------------------------------*/