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83 lines
3.4 KiB
C++
83 lines
3.4 KiB
C++
// Copyright 2024 The Chromium Authors
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// Use of this source code is governed by a BSD-style license that can be
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// found in the LICENSE file.
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#ifndef BASE_SYNCHRONIZATION_LOCK_SUBTLE_H_
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#define BASE_SYNCHRONIZATION_LOCK_SUBTLE_H_
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#include "base/base_export.h"
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#include "base/containers/span.h"
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#include "base/dcheck_is_on.h"
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#include "base/notreached.h"
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#include "build/build_config.h"
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namespace base::subtle {
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#if DCHECK_IS_ON()
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// Returns addresses of locks acquired by the current thread with
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// `subtle::LockTracking::kEnabled`. `uintptr_t` is used because addresses are
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// meant to be used as unique identifiers but not to be dereferenced.
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BASE_EXPORT span<const uintptr_t> GetTrackedLocksHeldByCurrentThread();
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#endif
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// Whether to add a lock to the list returned by
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// `subtle::GetLocksHeldByCurrentThread()` upon acquisition. This has no effect
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// in non-DCHECK builds because tracking is always disabled. This is disabled by
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// default to avoid exceeding the fixed-size storage backing
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// `GetTrackedLocksHeldByCurrentThread()` and to avoid reentrancy, e.g.:
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//
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// thread_local implementation
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// Add lock to the thread_local array of locks held by current thread
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// base::Lock::Acquire from allocator shim
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// ... Allocator shim ...
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// thread_local implementation
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// Access to a thread_local variable
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//
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// A lock acquired with `subtle::LockTracking::kEnabled` can be used to provide
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// a mutual exclusion guarantee for SEQUENCE_CHECKER.
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enum class LockTracking {
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kDisabled,
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kEnabled,
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};
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// YieldProcessor() wraps an architecture specific-instruction that informs the
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// processor the thread in a busy wait, which can reduce power consumption and
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// improve performance.
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static inline void YieldProcessor() {
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#if defined(ARCH_CPU_X86_64) || defined(ARCH_CPU_X86)
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__asm__ __volatile__("pause");
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#elif (defined(ARCH_CPU_ARMEL) && __ARM_ARCH >= 6) || defined(ARCH_CPU_ARM64)
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__asm__ __volatile__("yield");
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#elif defined(ARCH_CPU_MIPSEL)
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// The MIPS32 docs state that the PAUSE instruction is a no-op on older
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// architectures (first added in MIPS32r2). To avoid assembler errors when
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// targeting pre-r2, we must encode the instruction manually.
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__asm__ __volatile__(".word 0x00000140");
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#elif defined(ARCH_CPU_MIPS64EL) && __mips_isa_rev >= 2
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// Don't bother doing using .word here since r2 is the lowest supported mips64
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// that Chromium supports.
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__asm__ __volatile__("pause");
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#elif defined(ARCH_CPU_PPC64_FAMILY)
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__asm__ __volatile__("or 31,31,31");
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#elif defined(ARCH_CPU_RISCV64)
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// Zihintpause extension provides a pause instruction but that extension
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// is not included in the current rv64gc baseline. However, the pause
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// instruction is encoded as a hint. Thus on CPUs without Zihintpause
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// extension, the pause instruction is treated like a nop.
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// Manually encode the instruction to support older toolchains.
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// See also https://sourceware.org/pipermail/libc-alpha/2024-June/157737.html
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__asm__ __volatile__(".insn i 0x0f, 0, x0, x0, 0x010");
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#elif defined(ARCH_CPU_LOONGARCH_FAMILY)
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// LoongArch does not have a semantic instruction to actively relinquish
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// resources in the multi threads. In terms of backoff for spin locks,
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// LoongArch's LL/SC instruction comes with random delay and generally does not
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// require additional software implementation.
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NOTREACHED();
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#else
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#endif // ARCH
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}
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} // namespace base::subtle
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#endif // BASE_SYNCHRONIZATION_LOCK_SUBTLE_H_
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