Files
esp-idf/components/esp_system/system_init_fn.txt
Guillaume Souchere 9835daba70 feat(freertos/vfs): add Linux cooperative syscall dispatch with VFS FD registration
Rework the syscall interposition architecture so FreeRTOS works
standalone (without VFS) and VFS optionally overrides with strong
symbols.  All kernel FDs are registered with VFS via
esp_vfs_register_fd_with_local_fd, so the application only sees
VFS-allocated FD numbers, preventing numerical collisions between
kernel FDs and VFS-internal FD slots.

FreeRTOS side:
- Create linux_port_coop_internal.h with LINUX_COOP_IO_LOOP,
  LINUX_COOP_RESOLVE, linux_coop_yield and FD state table functions
- Export cooperative I/O primitives (freertos_linux_coop_read/write/
  open/close/fcntl/select/pread/pwrite/readv/writev/recv/send/
  recvfrom/sendto/recvmsg/sendmsg/connect/accept/pselect/poll/
  socket/socketpair/pipe/pipe2/dup/dup2/syscalls_init)
- Define weak POSIX symbols calling through to the cooperative
  primitives; keep nanosleep/sleep/usleep as strong (not FD-related)
- Refactor freertos_linux_coop_syscalls.h into a pure public API header

VFS side:
- Register the Linux host FS with esp_vfs_register_fs_with_id() as a
  proper VFS driver; register stdin/stdout/stderr at init (priority 99)
- Rewrite vfs_linux.c with strong POSIX symbols dispatching through
  esp_vfs_*
- Add strong overrides for FD-creating syscalls (open, pipe, pipe2,
  socket, socketpair, dup, dup2, accept) that register returned FDs
  with VFS
- Add strong overrides for FD-translating syscalls (readv, writev,
  recv, send, recvfrom, sendto, recvmsg, sendmsg, connect, pselect,
  poll) that translate VFS FD to kernel FD
- Delete vfs_coop_syscalls.c (absorbed into FreeRTOS weak + VFS strong)
- Update CMakeLists.txt: remove vfs_coop_syscalls.c, add linker hook
2026-06-04 11:36:34 +02:00

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# This file documents the expected order of execution of ESP_SYSTEM_INIT_FN functions.
#
# When adding new ESP_SYSTEM_INIT_FN functions or changing init priorities of existing functions,
# keep this file up to date. This is checked in CI.
# When adding new functions or changing the priorities, please read the comments and see if
# they need to be updated to be consistent with the changes you are making.
#
# Entries are ordered by the order of execution (i.e. from low priority values to high ones).
# Each line has the following format:
# stage: prio: function_name in path/to/source_file on affinity_expression
# Where:
# stage: which startup stage the function is executed in (CORE or SECONDARY)
# prio: priority value (higher value means function is executed later)
# affinity_expression: bit map of cores the function is executed on
########### CORE startup stage ###########
# [refactor-todo]: move init calls into respective components
CORE: 1: init_efuse_check in components/efuse/src/esp_efuse_startup.c on BIT(0)
# Log some information about the system
CORE: 10: init_show_cpu_freq in components/esp_system/startup_funcs.c on BIT(0)
CORE: 20: init_show_app_info in components/esp_app_format/esp_app_desc.c on BIT(0)
CORE: 21: init_efuse_show_app_info in components/efuse/src/esp_efuse_startup.c on BIT(0)
# Set the standard stream to non blocking and register the default vfs
CORE: 99: init_vfs_linux_coop in components/vfs/vfs_linux_default_coop.c on BIT(0)
# Initialize heap allocator. WARNING: This *needs* to happen *after* the app cpu has booted.
# If the heap allocator is initialized first, it will put free memory linked list items into
# memory also used by the ROM. Starting the app cpu will let its ROM initialize that memory,
# corrupting those linked lists. Initializing the allocator *after* the app cpu has booted
# works around this problem.
# With SPI RAM enabled, there's a second reason: half of the SPI RAM will be managed by the
# app CPU, and when that is not up yet, the memory will be inaccessible and heap_caps_init may
# fail initializing it properly.
CORE: 100: init_heap in components/heap/heap_caps_init.c on BIT(0)
# When apptrace module is enabled, there will be SEGGER_SYSVIEW calls in the esp_libc init.
# SEGGER_SYSVIEW relies on apptrace module
# apptrace module uses esp_timer_get_time to determine timeout conditions.
# esp_timer early initialization is required for esp_timer_get_time to work.
CORE: 101: esp_timer_init_nonos in components/esp_timer/src/esp_timer_init.c on BIT(0)
CORE: 102: init_libc in components/esp_libc/src/init.c on BIT(0)
# PSRAM core stage init, including
# - Add the psram to heap, psram vaddr region is reserved when initialising the heap, after
# psram is initialised (and necessary reservation for psram usage), the rest of the psram
# will be added to the heap
# - Register PSRAM ISR routine
CORE: 103: psram_core_stage_init in components/esp_psram/system_layer/esp_psram.c on BIT(0)
CORE: 105: init_brownout in components/esp_system/startup_funcs.c on BIT(0)
CORE: 106: init_libc_time in components/esp_libc/src/init.c on BIT(0)
# Peripheral-specific implementation operators should be filled first
# Then register vfs console, and follow by esp_libc stdio initialization
CORE: 110: init_vfs_uart in components/esp_driver_uart/src/uart_vfs.c on BIT(0)
CORE: 111: init_vfs_usj in components/esp_driver_usb_serial_jtag/src/usb_serial_jtag_vfs.c on BIT(0)
CORE: 112: init_vfs_usj_sec in components/esp_driver_usb_serial_jtag/src/usb_serial_jtag_vfs.c on BIT(0)
CORE: 113: init_vfs_usb_cdc_rom_console in components/esp_usb_cdc_rom_console/vfs_cdcacm.c on BIT(0)
CORE: 118: init_vfs_nullfs in components/vfs/nullfs.c on BIT(0)
CORE: 119: init_vfs_console in components/esp_stdio/stdio_vfs.c on BIT(0)
CORE: 120: init_libc_stdio in components/esp_libc/src/init.c on BIT(0)
CORE: 130: init_flash in components/spi_flash/esp_flash_spi_init.c on BIT(0)
CORE: 140: init_efuse in components/efuse/src/esp_efuse_startup.c on BIT(0)
CORE: 170: init_xt_wdt in components/esp_system/startup_funcs.c on BIT(0)
########### SECONDARY startup stage ###########
# esp_timer has to be initialized early, since it is used by several other components
SECONDARY: 100: esp_timer_init_os in components/esp_timer/src/esp_timer.c on ESP_TIMER_INIT_MASK
# Assist-debug early init for stack guard and PC recording.
SECONDARY: 101: esp_hw_debug_assist_init in components/esp_system/debug_assist.c on ESP_SYSTEM_INIT_ALL_CORES
# Initialize RNG (enable clock which is disabled in `esp_perip_clk_init`, configure entropy sources)
SECONDARY: 102: init_rng in components/esp_hw_support/hw_random.c on BIT(0)
# Security specific initializations
SECONDARY: 103: esp_security_init in components/esp_security/src/init.c on BIT(0)
# PSA Crypto initialization (must happen after esp_security_init for hardware crypto support)
SECONDARY: 104: mbedtls_psa_crypto_init_fn in components/mbedtls/port/esp_psa_crypto_init.c on BIT(0)
# esp_sleep doesn't have init dependencies
SECONDARY: 105: esp_sleep_startup_init in components/esp_hw_support/sleep_gpio.c on BIT(0)
SECONDARY: 106: sleep_clock_startup_init in components/esp_hw_support/lowpower/port/esp32c5/sleep_clock.c on BIT(0)
SECONDARY: 106: sleep_clock_startup_init in components/esp_hw_support/lowpower/port/esp32c6/sleep_clock.c on BIT(0)
SECONDARY: 106: sleep_clock_startup_init in components/esp_hw_support/lowpower/port/esp32c61/sleep_clock.c on BIT(0)
SECONDARY: 106: sleep_clock_startup_init in components/esp_hw_support/lowpower/port/esp32h2/sleep_clock.c on BIT(0)
SECONDARY: 106: sleep_clock_startup_init in components/esp_hw_support/lowpower/port/esp32h21/sleep_clock.c on BIT(0)
SECONDARY: 106: sleep_clock_startup_init in components/esp_hw_support/lowpower/port/esp32h4/sleep_clock.c on BIT(0)
SECONDARY: 106: sleep_clock_startup_init in components/esp_hw_support/lowpower/port/esp32p4/sleep_clock.c on BIT(0)
SECONDARY: 106: sleep_clock_startup_init in components/esp_hw_support/lowpower/port/esp32s31/sleep_clock.c on BIT(0)
SECONDARY: 106: sleep_clock_icg_startup_init in components/esp_hw_support/port/esp32p4/pmu_sleep_clock_icg.c on BIT(0)
SECONDARY: 107: sleep_sys_periph_startup_init in components/esp_hw_support/sleep_system_peripheral.c on BIT(0)
SECONDARY: 108: sleep_power_startup_init in components/esp_hw_support/lowpower/port/esp32h4/sleep_power.c on BIT(0)
# app_trace doesn't have init dependencies
SECONDARY: 115: apptrace_early_init in components/app_trace/app_trace.c on ESP_SYSTEM_INIT_ALL_CORES
# esp_trace doesn't have init dependencies
SECONDARY: 120: esp_trace_early_init in components/esp_trace/src/core/esp_trace_core.c on ESP_SYSTEM_INIT_ALL_CORES
# coredump doesn't have init dependencies
SECONDARY: 130: init_coredump in components/espcoredump/src/core_dump_init.c on BIT(0)
# esp_debug_stubs doesn't have init dependencies
SECONDARY: 140: init_dbg_stubs in components/app_trace/debug_stubs.c on BIT(0)
# Register NVS Encryption schemes
SECONDARY: 150: nvs_sec_provider_register_flash_enc_scheme in components/nvs_sec_provider/nvs_sec_provider.c on BIT(0)
SECONDARY: 151: nvs_sec_provider_register_hmac_scheme in components/nvs_sec_provider/nvs_sec_provider.c on BIT(0)
# the rest of the components which are initialized from startup_funcs.c
# [refactor-todo]: move init calls into respective components
SECONDARY: 201: init_pm in components/esp_system/startup_funcs.c on BIT(0)
SECONDARY: 202: init_pm_flash_freq_limit in components/esp_pm/pm_c5_flash_freq_limit.c on BIT(0)
SECONDARY: 203: init_apb_dma in components/esp_system/startup_funcs.c on BIT(0)
SECONDARY: 204: init_coexist in components/esp_coex/src/coexist.c on BIT(0)
SECONDARY: 205: init_bootloader_offset in components/esp_system/startup_funcs.c on BIT(0)
# usb_console needs to create an esp_timer at startup.
# This can be done only after esp_timer initialization (esp_timer_init_os).
SECONDARY: 220: esp_usb_console_init_restart_timer in components/esp_usb_cdc_rom_console/usb_console.c on BIT(0)
# usb_serial_jtag needs to create and acquire a PM lock at startup.
# This makes more sense to be done after esp_pm_impl_init (called from init_pm).
SECONDARY: 230: usb_serial_jtag_conn_status_init in components/esp_driver_usb_serial_jtag/src/usb_serial_jtag_connection_monitor.c on BIT(0)
# psram adjust timing point need a separate task which should be created at startup.
# Valid only `CONFIG_SPIRAM_TIMING_TUNING_POINT_VIA_TEMPERATURE_SENSOR` is enabled.
SECONDARY: 240: psram_adjust_timing_point_via_temperature in components/esp_hw_support/mspi/mspi_timing_tuning/port/esp32s3/mspi_timing_by_mspi_delay.c on BIT(0)
# Has to be the last step!
# Now that the application is about to start, disable boot watchdog
SECONDARY: 999: init_disable_rtc_wdt in components/esp_system/startup_funcs.c on BIT(0)
# DO NOT add new init functions here. Add them to the correct stage above.