morris f5afb99e3b fix(gdma): treat burst size 0 and 1 as burst disabled ...

The GDMA layer used `max_data_burst_size == 0` as the only way to disable the
data burst. That conflicts with the upstream drivers' convention where a zeroed
config struct means "unset", so users had no way to ask for the driver default
burst size.

GDMA now treats both 0 and 1 as "no data burst": a single-beat burst has no
benefit over the non-burst mode. The MSPI alignment constraint under Flash
Encryption / PSRAM ECC still takes precedence and is reported with a warning.

The upstream drivers using GDMA now apply their own default burst size (16
bytes) when the user leaves `dma_burst_size` as 0, following the UHCI driver:

- esp_async_crc (AHB / AXI GDMA backend)
- esp_async_memcpy (AHB / AXI / LP-AHB / DW_GDMA backend)

Callers that really want no burst can now set `dma_burst_size` to 1.

2026-09-08 23:29:14 +08:00

..

i3c_master_i2c.h

feat(i3c): Add example for i2c mode in i3c peripheral

2025-07-21 19:23:29 +08:00

i3c_master_types.h

feat(i3c): Support i3c master functions on esp32p4

2025-12-31 18:04:25 +08:00

i3c_master.h

fix(gdma): treat burst size 0 and 1 as burst disabled

2026-09-08 23:29:14 +08:00