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mirror of https://github.com/espressif/esp-idf.git synced 2026-06-05 20:56:32 +03:00
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ed033b1700a13bb2ba5b0f4e43e9121a98d44965
esp-idf/components/ulp/ulp_riscv
History
He Binglin 1b547ca0ba Merge branch 'bugfix/esp_idf_s3_deepsleep_dead' into 'master'
fix(hal): fix the issue of dual-core contention for RTC_CNTL regs

See merge request espressif/esp-idf!41680
2026-03-02 11:35:53 +08:00
..
include
refactor(ulp_riscv): Modify ulp i2c read/write functions to return error code
2025-08-20 14:16:44 +05:30
shared/include
ulp-riscv: added lock API to provide mutual exclusion when sharing variables between the main CPU and the ULP.
2022-08-05 18:16:31 +08:00
ulp_core
fix(ulp): correct ULP LP and RISCV interrupt wait cycle duration
2026-02-19 13:32:31 +05:30
ulp_riscv_i2c.c
fix(ulp): correct ULP LP and RISCV interrupt wait cycle duration
2026-02-19 13:32:31 +05:30
ulp_riscv_lock.c
ulp-riscv: added lock API to provide mutual exclusion when sharing variables between the main CPU and the ULP.
2022-08-05 18:16:31 +08:00
ulp_riscv.c
fix(hal): fix the issue of dual-core contention for RTC_CNTL regs
2026-02-10 12:08:03 +08:00
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