Michael (XIAO Xufeng) 3a0f7e9ceb Merge branch 'bugfix/c5_add_freq_restriction_again' into 'master' ...

fix(esp_system): limit CPU clock to 160MHz in ESP32-C5 for flash encryption

See merge request espressif/esp-idf!44498

2026-02-10 11:42:38 +08:00

..

arch

refactor: avoid function calls inside MIN/MAX macros

2025-11-17 22:17:54 +08:00

include

feat(esp_tee): Add support for the RISC-V H/W stack guard mechanism

2025-11-24 18:49:06 +05:30

soc

Merge branch 'bugfix/c5_add_freq_restriction_again' into 'master'

2026-02-10 11:42:38 +08:00

CMakeLists.txt

fix(clk): 400MHz CPU should still be selectable on ESP32-P4 less than rev3

2025-11-11 17:03:25 +08:00

cpu_start.c

Merge branch 'feature/esp32c61_flash_psram_timing_tuning' into 'master'

2026-01-22 16:36:25 +08:00

esp_ipc_isr.c

feat(esp_system): Adds Kconfigs to place code in IRAM

2025-06-23 13:23:33 +03:00

esp_system_chip.c

refactor(uart)!: deprcated esp_rom_uart.h

2025-07-08 18:56:17 +08:00

esp_system_linux.c

refactor(system): removed esp_system from astyle ignore list and reformated it

2024-01-30 15:17:15 +08:00

image_process.c

feat(psram): xip psram c5

2024-09-03 18:17:03 +08:00

panic_handler.c

remove(esp_hw_support): Remove redundant and unsupported memprot mentions

2025-08-04 11:43:01 +05:30