Omar Chebib c27c33a832 fix(riscv): implement a workaround for Zcmp hardware bug

2026-04-10 15:03:09 +08:00

..

include

fix(riscv): implement a workaround for Zcmp hardware bug

2026-04-10 15:03:09 +08:00

ld

refactor(riscv): added a new API for the interrupts

2024-01-18 16:36:53 +08:00

CMakeLists.txt

feat(esp_tee): Support for ESP32-C5 - the rest of the components

2025-08-13 14:08:59 +05:30

instruction_decode.c

refactor(tools): Tidy up core component files copyright ignore

2024-01-22 18:07:35 +08:00

interrupt_clic.c

fix(riscv): implement a workaround for Zcmp hardware bug

2026-04-10 15:03:09 +08:00

interrupt_intc.c

refactor(riscv): added a new API for the interrupts

2024-01-18 16:36:53 +08:00

interrupt_plic.c

refactor(esp_tee): Revised the secure service ID numbering scheme

2025-01-23 12:39:19 +05:30

interrupt.c

feat(intr): basic interrupt/freertos support for C61

2024-06-12 09:25:47 +08:00

linker.lf

refactor(esp32c61): bus_monitor backward compatible refactor

2025-04-08 22:50:04 +08:00

rv_utils.c

refactor(esp32c61): bus_monitor backward compatible refactor

2025-04-08 22:50:04 +08:00

vectors_clic.S

change(riscv): Remove redundant definition of MEMPROT_ISR

2025-08-04 11:43:01 +05:30

vectors_intc.S

refactor(esp_system): Update all references of the memory protection configs

2025-08-04 11:43:01 +05:30

vectors.S

fix(riscv): implement a workaround for Zcmp hardware bug

2026-04-10 15:03:09 +08:00