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e16593ebc0
GCC 16 flags the volatile accumulator in the cache writeback loops even though it is volatile, as it is only used to update itself. Drop the accumulator and rely on the volatile-qualified psram pointer to keep the cache-line reads from being optimized out.
79 lines
2.9 KiB
C
79 lines
2.9 KiB
C
/*
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* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "soc/dport_reg.h"
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#include "esp_attr.h"
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#include "esp_psram.h"
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#include "esp_private/esp_psram_extram.h"
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#if CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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#define PSRAM_MODE PSRAM_VADDR_MODE_NORMAL
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#else
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#define PSRAM_MODE PSRAM_VADDR_MODE_LOWHIGH
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#endif
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/*
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Before flushing the cache, if psram is enabled as a memory-mapped thing, we need to write back the data in the cache to the psram first,
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otherwise it will get lost. For now, we just read 64/128K of random PSRAM memory to do this.
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Note that this routine assumes some unique mapping for the first 2 banks of the PSRAM memory range, as well as the
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2 banks after the 2 MiB mark.
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*/
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void IRAM_ATTR esp_psram_extram_writeback_cache(void)
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{
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int x;
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volatile uint8_t *psram = (volatile uint8_t*)SOC_EXTRAM_DATA_LOW;
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int cache_was_disabled = 0;
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if (!esp_psram_is_initialized()) {
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return;
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}
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//We need cache enabled for this to work. Re-enable it if needed; make sure we
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//disable it again on exit as well.
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if (DPORT_REG_GET_BIT(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_CACHE_ENABLE) == 0) {
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cache_was_disabled |= (1 << 0);
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DPORT_SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL_REG, 1, 1, DPORT_PRO_CACHE_ENABLE_S);
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}
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#ifndef CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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if (DPORT_REG_GET_BIT(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_CACHE_ENABLE) == 0) {
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cache_was_disabled |= (1 << 1);
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DPORT_SET_PERI_REG_BITS(DPORT_APP_CACHE_CTRL_REG, 1, 1, DPORT_APP_CACHE_ENABLE_S);
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}
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#endif
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#if (PSRAM_MODE != PSRAM_VADDR_MODE_LOWHIGH)
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/*
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Single-core and even/odd mode only have 32K of cache evenly distributed over the address lines. We can clear
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the cache by just reading 64K worth of cache lines.
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*/
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for (x = 0; x < 1024 * 64; x += 32) {
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(void)psram[x];
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}
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#else
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/*
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Low/high psram cache mode uses one 32K cache for the lowest 2MiB of SPI flash and another 32K for the highest
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2MiB. Clear this by reading from both regions.
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Note: this assumes the amount of external RAM is >2M. If it is 2M or less, what this code does is undefined. If
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we ever support external RAM chips of 2M or smaller, this may need adjusting.
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*/
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for (x = 0; x < 1024 * 64; x += 32) {
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(void)psram[x];
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(void)psram[x + (1024 * 1024 * 2)];
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}
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#endif
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if (cache_was_disabled & (1 << 0)) {
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while (DPORT_GET_PERI_REG_BITS2(DPORT_PRO_DCACHE_DBUG0_REG, DPORT_PRO_CACHE_STATE, DPORT_PRO_CACHE_STATE_S) != 1) ;
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DPORT_SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL_REG, 1, 0, DPORT_PRO_CACHE_ENABLE_S);
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}
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#ifndef CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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if (cache_was_disabled & (1 << 1)) {
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while (DPORT_GET_PERI_REG_BITS2(DPORT_APP_DCACHE_DBUG0_REG, DPORT_APP_CACHE_STATE, DPORT_APP_CACHE_STATE_S) != 1);
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DPORT_SET_PERI_REG_BITS(DPORT_APP_CACHE_CTRL_REG, 1, 0, DPORT_APP_CACHE_ENABLE_S);
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}
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#endif
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}
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