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198 lines
8.5 KiB
Plaintext
198 lines
8.5 KiB
Plaintext
menu "Ultra Low Power (ULP) Co-processor"
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depends on (SOC_ULP_SUPPORTED || SOC_RISCV_COPROC_SUPPORTED || SOC_LP_CORE_SUPPORTED)
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config ULP_COPROC_ENABLED
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bool "Enable Ultra Low Power (ULP) Co-processor"
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default "n"
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help
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Enable this feature if you plan to use the ULP Co-processor.
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Once this option is enabled, further ULP co-processor configuration will appear in the menu.
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menu "ULP Coprocessor types"
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depends on ULP_COPROC_ENABLED
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config ULP_COPROC_TYPE_FSM
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bool "ULP FSM (Finite State Machine)"
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depends on SOC_ULP_FSM_SUPPORTED
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default y if IDF_TARGET_ESP32
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config ULP_COPROC_TYPE_RISCV
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bool "ULP RISC-V"
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depends on SOC_RISCV_COPROC_SUPPORTED
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default y if (IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3) && !ULP_COPROC_TYPE_FSM
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config ULP_COPROC_TYPE_LP_CORE
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bool "LP core RISC-V"
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depends on SOC_LP_CORE_SUPPORTED
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default y if (!IDF_TARGET_ESP32 && !IDF_TARGET_ESP32S2 && !IDF_TARGET_ESP32S3)
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endmenu
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config ULP_COPROC_RESERVE_MEM
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int
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prompt "RTC slow memory reserved for coprocessor"
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depends on ULP_COPROC_ENABLED
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default 512 if IDF_TARGET_ESP32
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default 4096 if !IDF_TARGET_ESP32
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range 32 8176 if IDF_TARGET_ESP32 || IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3
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range 32 16352 if IDF_TARGET_ESP32C5 || IDF_TARGET_ESP32C6
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range 32 32744 if IDF_TARGET_ESP32S31
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range 32 31088 if IDF_TARGET_ESP32P4 # Some memory are reserved for ROM/RTC reserved
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help
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Bytes of memory to reserve for ULP Co-processor firmware & data.
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Data is reserved at the beginning of RTC slow memory.
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The target-specific maximum only accounts for fixed LP/RTC reservations
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such as retained RTC data, LP ROM, and secure-boot digest storage.
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On targets where the application RTC sections also live in LP/RTC RAM,
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this reservation shares the same memory pool with .rtc.text,
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RTC_DATA_ATTR, RTC_NOINIT_ATTR, RTC_SLOW_ATTR, and related sections.
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Setting this value close to the maximum may therefore still leave too
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little LP/RTC RAM for the rest of the application and cause link-time
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errors.
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menu "ULP RISC-V Settings"
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depends on ULP_COPROC_TYPE_RISCV
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config ULP_RISCV_INTERRUPT_ENABLE
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bool
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prompt "Enable ULP RISC-V interrupts"
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default "n"
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help
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Turn on this setting to enabled interrupts on the ULP RISC-V core.
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config ULP_RISCV_UART_BAUDRATE
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int
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prompt "Baudrate used by the bitbanged ULP RISC-V UART driver"
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default 9600
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help
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The accuracy of the bitbanged UART driver is limited, it is not
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recommend to increase the value above 19200.
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config ULP_RISCV_I2C_RW_TIMEOUT
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int
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prompt "Set timeout for ULP RISC-V I2C transaction timeout in ticks."
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default 500
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range -1 4294967295
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help
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Set the ULP RISC-V I2C read/write timeout. Set this value to -1
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if the ULP RISC-V I2C read and write APIs should wait forever.
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Please note that the tick rate of the ULP co-processor would be
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different than the OS tick rate of the main core and therefore
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can have different timeout value depending on which core the API
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is invoked on.
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endmenu
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config ULP_SHARED_MEM
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depends on ULP_COPROC_TYPE_LP_CORE
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hex
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default 0x10
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help
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Size of the shared memory defined in ulp_lp_core_memory_shared.c.
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Size should be kept in-sync with the size of the struct defined there.
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menu "LP Core HP Memory"
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depends on ULP_COPROC_TYPE_LP_CORE
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config ULP_COPROC_RUN_FROM_HP_MEM
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bool "Run LP Core from HP memory"
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depends on !SECURE_ENABLE_TEE
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default n
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help
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Enable this option to allow the LP Core application to use HP SRAM for
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code and data. This allows much larger LP Core applications than would
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fit in LP RAM.
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Note: When this option is enabled, the LP Core cannot run during deep
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sleep because HP SRAM is powered off during sleep.
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config ULP_COPROC_RESERVE_HP_MEM_BYTES
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hex "HP SRAM size reserved for LP Core (bytes)"
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depends on ULP_COPROC_RUN_FROM_HP_MEM
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default 0x10000
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range 0x1000 0x80000
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help
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Amount of HP SRAM (in bytes) to carve out from the top of the HP SRAM
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region for the LP Core application. This memory is not available to the
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HP application.
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endmenu
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config ULP_ROM_PRINT_ENABLE
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depends on ULP_COPROC_TYPE_LP_CORE && ESP_ROM_HAS_LP_ROM
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bool
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prompt "Enable print utilities from LP ROM"
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default "y"
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help
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Set this option to enable printf functionality from LP ROM. This option
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can help reduce the LP core binary size by not linking printf functionality
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from RAM code.
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Note: For LP ROM prints to work properly, make sure that the LP core boots
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from the LP ROM.
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config ULP_LP_CORE_MEMPROT
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bool "Enable LP Core memory protection (PMP)"
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depends on ULP_COPROC_TYPE_LP_CORE && SOC_LP_CORE_HAS_PMP && !ULP_COPROC_RUN_FROM_HP_MEM
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default n
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help
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Configures the LP CPU's PMP entries to enforce memory protection.
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LP RAM is split into executable (.text) and data (.data/.bss/stack)
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regions. Regions not explicitly permitted are inaccessible.
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Not available when "Run LP Core from HP memory" is enabled.
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Disable this if you need full control over PMP configuration.
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config ULP_TRAP_WAKEUP
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depends on ULP_COPROC_TYPE_LP_CORE
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bool
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prompt "Enable wakeup of HP-CPU when LP-core encounters an exception"
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default "y"
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help
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Set this option to also trigger a wakeup signal to the HP-CPU when
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the LP-core encounters an exception.
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menu "ULP Debugging Options"
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config ULP_PANIC_OUTPUT_ENABLE
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depends on ULP_COPROC_TYPE_LP_CORE && SOC_ULP_LP_UART_SUPPORTED
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bool
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prompt "Enable panic handler which outputs over LP UART"
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default "n"
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help
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Set this option to enable panic handler functionality. If this option is
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enabled then the LP Core will output a panic dump over LP UART,
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similar to what the main core does. Output depends on LP UART already being
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initialized and configured.
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Disabling this option will reduce the LP core binary size by not
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linking in panic handler functionality.
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config ULP_HP_UART_CONSOLE_PRINT
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depends on ULP_COPROC_TYPE_LP_CORE
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bool
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prompt "Route lp_core_printf to the console HP-UART"
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help
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Set this option to route lp_core_printf to the console HP-UART.
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This allows you to easily view print outputs from the LP core, without
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having to connect to the LP-UART. This option comes with the following
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limitations:
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1. There is no mutual exclusion between the HP-Core and the LP-Core accessing
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the HP-UART, which means that if both cores are logging heavily the output
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strings might get mangled together.
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2. The HP-UART can only work while the HP-Core is running, which means that
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if the HP-Core is in deep sleep, the LP-Core will not be able to print to the
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console HP-UART.
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Due to these limitations it is only recommended to use this option for easy debugging.
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For more serious use-cases you should use the LP-UART.
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config ULP_NORESET_UNDER_DEBUG
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bool "Avoid resetting LP core when debugger is attached"
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depends on ULP_COPROC_TYPE_LP_CORE
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default "y"
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help
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Enable this feature to avoid resetting LP core in sleep mode when debugger is attached,
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otherwise configured HW breakpoints and dcsr.ebreak* bits will be missed.
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This is a workaround until it will be fixed in HW.
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endmenu
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endmenu # Ultra Low Power (ULP) Co-processor
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