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758cf6e1a3
This commit refactors the SPI flash component to improve encapsulation and
modularity by moving internal types and functions to private headers, and
reorganizing initialization code.
Key changes:
1. Move PSRAM frequency constraint macro from soc_caps.h to mspi_ll.h
- Rename SOC_SPI_MEM_PSRAM_FREQ_AXI_CONSTRAINED to
MSPI_TIMING_LL_PSRAM_FREQ_AXI_CONSTRAINED
- Move macro definition to chip-specific mspi_ll.h files (C5, C61, H4, P4, S31)
- Update usage in clk_utils.c and esp_flash_spi_init.c
- Remove old macro from all soc_caps.h files
2. Move internal types to private headers
- Move esp_flash_t structure to esp_private/esp_flash_types.h
- Move esp_flash_os_functions_t to esp_private/spi_flash_os.h
- Update all internal files to include private headers
- Keep forward declarations in public esp_flash.h
3. Move chip driver header to internal directory
- Move spi_flash_chip_driver.h to esp_flash_port/spi_flash_chip_driver.h
- Update all references to use new path
- Add esp_private/esp_flash_types.h include to the moved header
4. Refactor initialization functions
- Move init_flash from esp_system/startup_funcs.c to
spi_flash/esp_flash_spi_init.c
- Create new init_pm_flash_freq_limit function in startup_funcs.c
to call esp_pm_flash_freq_limit_init() conditionally
- Update system_init_fn.txt with new function locations
5. Improve API encapsulation
- Replace direct access to esp_flash_t->size in
esp_partition_register_external() with esp_flash_get_size() API
- Move esp_flash_is_quad_mode from inline function to regular function
in esp_flash_api.c
6. Update component dependencies
- Add esp_driver_gpio to spi_flash component PRIV_REQUIRES
- Remove unused includes and clean up header dependencies
These changes improve code organization by clearly separating public APIs
from internal implementation details, making the codebase more maintainable
and reducing the risk of breaking changes to internal structures.
75 lines
2.8 KiB
C
75 lines
2.8 KiB
C
/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <sys/param.h>
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#include <inttypes.h>
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#include <string.h>
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#include <assert.h>
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#include "sdkconfig.h"
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#include "esp_check.h"
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#include "esp_log.h"
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#include "soc/rtc.h"
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#include "hal/mspi_ll.h"
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#include "hal/clk_tree_ll.h"
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#include "esp_private/mspi_timing_tuning.h"
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#include "esp_private/esp_clk_utils.h"
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// Not directly divide to avoid truncation issue
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// DIG-498
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#if CONFIG_IDF_TARGET_ESP32P4
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#define BELOW_FREQ_THRESHOLD(freq) ((freq) < CONFIG_SPIRAM_SPEED)
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#elif CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61 || CONFIG_IDF_TARGET_ESP32H4
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#define BELOW_FREQ_THRESHOLD(freq) ((freq) * 8 < CONFIG_SPIRAM_SPEED)
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#elif CONFIG_IDF_TARGET_ESP32S31
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#define BELOW_FREQ_THRESHOLD(freq) ((freq) * 4 < CONFIG_SPIRAM_SPEED * 3)
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#endif
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#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
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void esp_clk_utils_mspi_speed_mode_sync_before_cpu_freq_switching(uint32_t target_cpu_src_freq, uint32_t target_cpu_freq)
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{
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#if MSPI_TIMING_LL_FLASH_CPU_CLK_SRC_BINDED
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(void) target_cpu_freq;
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/* For ESP32S3, the clock source of MSPI is same as the CPU. When CPU use XTAL as clock source, we need to sync the
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* MSPI speed mode. */
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if (target_cpu_src_freq <= clk_ll_xtal_load_freq_mhz()) {
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mspi_timing_change_speed_mode_cache_safe(true);
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}
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#elif MSPI_TIMING_LL_PSRAM_FREQ_AXI_CONSTRAINED && CONFIG_SPIRAM
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/* On chips with AXI bus, currently there is a restriction that AXI frequency (usually equals to a portion of CPU
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* frequency) needs to be greater than or equal to MSPI PSRAM frequency to avoid writing MSPI FIFO overflow.
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*/
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if (BELOW_FREQ_THRESHOLD(target_cpu_freq)) {
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// Before switching to low speed mode, verify CPU frequency meets the constraint
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assert(target_cpu_freq >= mspi_timing_get_psram_low_speed_freq_mhz());
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mspi_timing_change_speed_mode_cache_safe(true);
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}
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#else
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(void) target_cpu_src_freq;
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(void) target_cpu_freq;
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#endif
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}
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void esp_clk_utils_mspi_speed_mode_sync_after_cpu_freq_switching(uint32_t target_cpu_src_freq, uint32_t target_cpu_freq)
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{
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#if MSPI_TIMING_LL_FLASH_CPU_CLK_SRC_BINDED
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(void) target_cpu_freq;
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if (target_cpu_src_freq > clk_ll_xtal_load_freq_mhz()) {
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mspi_timing_change_speed_mode_cache_safe(false);
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}
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#elif MSPI_TIMING_LL_PSRAM_FREQ_AXI_CONSTRAINED && CONFIG_SPIRAM
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/* On chips with AXI bus, currently there is a restriction that AXI frequency (usually equals to a portion of CPU
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* frequency) needs to be greater than or equal to MSPI PSRAM frequency to avoid writing MSPI FIFO overflow.
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*/
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if (!BELOW_FREQ_THRESHOLD(target_cpu_freq)) {
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mspi_timing_change_speed_mode_cache_safe(false);
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}
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#else
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(void) target_cpu_src_freq;
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(void) target_cpu_freq;
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#endif
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}
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#endif
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