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ee4f1deb85
Introduce SOC_USB_FSLS_PHY_NUM on ESP32-S2, ESP32-S3 and ESP32-P4 to expose the number of FSLS USB_WRAP PHYs available on each target. This separates FSLS USB_WRAP support from OTG/UTMI support so that downstream code can gate FSLS PHY handling independently.
soc
The soc component provides hardware description for targets supported by ESP-IDF.
- `xxx_reg.h` - defines registers related to the hardware
- `xxx_struct.h` - hardware description in C `struct`
- `xxx_channel.h` - definitions for hardware with multiple channels
- `xxx_caps.h` - features/capabilities of the hardware
- `xxx_pins.h` - pin definitions
- `xxx_periph.h/*.c` - includes all headers related to a peripheral; declaration and definition of IO mapping for that hardware
Specially, the xxx_reg.h and xxx_struct.h headers that generated by script are under register/soc folder. Please DO NOT add other manual coded files under this folder.
For other soc headers that are used as wrapper, definition, signaling, mapping or manual coded registers, please add them under include/soc folder.