mirror of
https://github.com/espressif/esp-idf.git
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radek.tandler
ce27a6e7e0
ECDSA enable pulses a reset that also holds SHA in reset, and SHA shares its DMA with AES. Key Manager enable pulses a reset that also covers the XTS-AES flash encryption key-usage selector. Neither path was serialized against those victims, so a hardware ECDSA/HMAC/DS operation could corrupt a concurrent SHA/AES transfer or an in-flight encrypted flash read. - Take the SHA/AES lock inside esp_crypto_ecdsa_lock_acquire(), before MPI, matching the DS lock order (sha_aes < mpi) - Add esp_crypto_key_mgr_enable_periph_clk_no_reset() and switch ECDSA, HMAC and DS to it; they only need the key-usage selector writable - Hold esp_crypto_key_manager_lock across those clock enable/disable pairs so selector writes stay serialized without resetting KM
240 lines
6.8 KiB
C
240 lines
6.8 KiB
C
/*
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* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <sys/lock.h>
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#include "esp_crypto_lock.h"
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/* Lock overview:
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SHA: peripheral independent, but DMA is shared with AES
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AES: peripheral independent, but DMA is shared with SHA
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MPI/RSA: independent
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ECC: independent
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HMAC: needs SHA
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DS: needs HMAC (which needs SHA), AES and MPI
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ECDSA: needs ECC and MPI, and its reset pulse holds SHA (and thus the SHA/AES DMA) in reset
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Key Manager: shared key-usage selectors (ECDSA/HMAC/DS/XTS-AES flash);
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esp_crypto_key_mgr_enable_periph_clk(true) resets it
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*/
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#if !NON_OS_BUILD
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#ifdef SOC_DIG_SIGN_SUPPORTED
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/* Lock for DS peripheral */
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static _lock_t s_crypto_ds_lock;
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#endif /* SOC_DIG_SIGN_SUPPORTED */
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#ifdef SOC_HMAC_SUPPORTED
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/* Lock for HMAC peripheral */
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static _lock_t s_crypto_hmac_lock;
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#endif /* SOC_HMAC_SUPPORTED */
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#ifdef SOC_MPI_SUPPORTED
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/* Lock for the MPI/RSA peripheral, also used by the DS peripheral */
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static _lock_t s_crypto_mpi_lock;
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#endif /* SOC_MPI_SUPPORTED */
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#if defined(SOC_SHA_SUPPORTED) || defined(SOC_AES_SUPPORTED)
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/* Single lock for SHA and AES, sharing a reserved GDMA channel */
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static _lock_t s_crypto_sha_aes_lock;
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#endif /* defined(SOC_SHA_SUPPORTED) || defined(SOC_AES_SUPPORTED) */
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#ifdef SOC_ECC_SUPPORTED
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/* Lock for ECC peripheral */
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static _lock_t s_crypto_ecc_lock;
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#endif /* SOC_ECC_SUPPORTED */
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#ifdef SOC_ECDSA_SUPPORTED
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/* Lock for ECDSA peripheral */
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static _lock_t s_crypto_ecdsa_lock;
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#if SOC_ECDSA_USES_MPI
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#include "hal/ecdsa_ll.h"
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#endif /* SOC_ECDSA_USES_MPI */
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#endif /* SOC_ECDSA_SUPPORTED */
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#if SOC_KEY_MANAGER_SUPPORT_KEY_DEPLOYMENT
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/* Lock for Key Manager peripheral */
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static _lock_t s_crypto_key_manager_lock;
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#endif /* SOC_KEY_MANAGER_SUPPORT_KEY_DEPLOYMENT */
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#ifdef SOC_HMAC_SUPPORTED
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void esp_crypto_hmac_lock_acquire(void)
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{
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_lock_acquire(&s_crypto_hmac_lock);
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esp_crypto_sha_aes_lock_acquire();
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}
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void esp_crypto_hmac_lock_release(void)
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{
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esp_crypto_sha_aes_lock_release();
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_lock_release(&s_crypto_hmac_lock);
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}
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#endif /* SOC_HMAC_SUPPORTED */
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#ifdef SOC_DIG_SIGN_SUPPORTED
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void esp_crypto_ds_lock_acquire(void)
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{
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_lock_acquire(&s_crypto_ds_lock);
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esp_crypto_hmac_lock_acquire();
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esp_crypto_mpi_lock_acquire();
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}
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void esp_crypto_ds_lock_release(void)
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{
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esp_crypto_mpi_lock_release();
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esp_crypto_hmac_lock_release();
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_lock_release(&s_crypto_ds_lock);
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}
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#endif /* SOC_DIG_SIGN_SUPPORTED */
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#if defined(SOC_SHA_SUPPORTED) || defined(SOC_AES_SUPPORTED)
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void esp_crypto_sha_aes_lock_acquire(void)
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{
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_lock_acquire(&s_crypto_sha_aes_lock);
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}
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void esp_crypto_sha_aes_lock_release(void)
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{
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_lock_release(&s_crypto_sha_aes_lock);
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}
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#endif /* defined(SOC_SHA_SUPPORTED) || defined(SOC_AES_SUPPORTED) */
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#if defined(SOC_SHA_CRYPTO_DMA) || defined(SOC_AES_CRYPTO_DMA)
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void esp_crypto_dma_lock_acquire(void)
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{
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_lock_acquire(&s_crypto_sha_aes_lock);
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}
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void esp_crypto_dma_lock_release(void)
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{
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_lock_release(&s_crypto_sha_aes_lock);
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}
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#endif /* defined(SOC_SHA_CRYPTO_DMA) || defined(SOC_AES_CRYPTO_DMA) */
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#ifdef SOC_MPI_SUPPORTED
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void esp_crypto_mpi_lock_acquire(void)
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{
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_lock_acquire(&s_crypto_mpi_lock);
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}
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void esp_crypto_mpi_lock_release(void)
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{
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_lock_release(&s_crypto_mpi_lock);
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}
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#endif /* SOC_MPI_SUPPORTED */
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#ifdef SOC_ECC_SUPPORTED
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void esp_crypto_ecc_lock_acquire(void)
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{
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_lock_acquire(&s_crypto_ecc_lock);
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}
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void esp_crypto_ecc_lock_release(void)
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{
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_lock_release(&s_crypto_ecc_lock);
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}
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#endif /* SOC_ECC_SUPPORTED */
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#ifdef SOC_ECDSA_SUPPORTED
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void esp_crypto_ecdsa_lock_acquire(void)
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{
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_lock_acquire(&s_crypto_ecdsa_lock);
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esp_crypto_ecc_lock_acquire();
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#if defined(SOC_SHA_SUPPORTED) || defined(SOC_AES_SUPPORTED)
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/* Enabling the ECDSA peripheral pulses the ECDSA reset
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(esp_crypto_ecdsa_enable_periph_clk() -> ecdsa_ll_reset_register()), and on every
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target that has an ECDSA peripheral that reset also holds SHA in reset: see the
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"otherwise SHA is held in reset" note in sha_ll_reset_register(). SHA shares its
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(G)DMA channel with AES, and the SHA/AES lock is what serializes both of them, so
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it has to be held across the pulse. Without it, a hardware ECDSA operation on one
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core lands in the middle of an unrelated SHA or AES transfer on the other core,
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which completes without an error but yields wrong output.
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Taken before the MPI lock to keep the acquisition order of
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esp_crypto_ds_lock_acquire() (SHA/AES before MPI) and avoid a lock cycle. */
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esp_crypto_sha_aes_lock_acquire();
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#endif /* defined(SOC_SHA_SUPPORTED) || defined(SOC_AES_SUPPORTED) */
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#ifdef SOC_ECDSA_USES_MPI
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if (ecdsa_ll_is_mpi_required()) {
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esp_crypto_mpi_lock_acquire();
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}
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#endif /* SOC_ECDSA_USES_MPI */
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}
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void esp_crypto_ecdsa_lock_release(void)
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{
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#ifdef SOC_ECDSA_USES_MPI
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if (ecdsa_ll_is_mpi_required()) {
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esp_crypto_mpi_lock_release();
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}
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#endif /* SOC_ECDSA_USES_MPI */
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#if defined(SOC_SHA_SUPPORTED) || defined(SOC_AES_SUPPORTED)
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esp_crypto_sha_aes_lock_release();
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#endif /* defined(SOC_SHA_SUPPORTED) || defined(SOC_AES_SUPPORTED) */
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esp_crypto_ecc_lock_release();
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_lock_release(&s_crypto_ecdsa_lock);
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}
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#endif /* SOC_ECDSA_SUPPORTED */
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#if SOC_KEY_MANAGER_SUPPORT_KEY_DEPLOYMENT
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void esp_crypto_key_manager_lock_acquire(void)
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{
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_lock_acquire(&s_crypto_key_manager_lock);
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}
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void esp_crypto_key_manager_lock_release(void)
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{
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_lock_release(&s_crypto_key_manager_lock);
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}
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#endif /* SOC_KEY_MANAGER_SUPPORT_KEY_DEPLOYMENT */
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#else /* NON_OS_BUILD */
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#ifdef SOC_HMAC_SUPPORTED
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void esp_crypto_hmac_lock_acquire(void) {}
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void esp_crypto_hmac_lock_release(void) {}
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#endif /* SOC_HMAC_SUPPORTED */
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#ifdef SOC_DIG_SIGN_SUPPORTED
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void esp_crypto_ds_lock_acquire(void) {}
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void esp_crypto_ds_lock_release(void) {}
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#endif /* SOC_DIG_SIGN_SUPPORTED */
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#if defined(SOC_SHA_SUPPORTED) || defined(SOC_AES_SUPPORTED)
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void esp_crypto_sha_aes_lock_acquire(void) {}
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void esp_crypto_sha_aes_lock_release(void) {}
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#endif /* defined(SOC_SHA_SUPPORTED) || defined(SOC_AES_SUPPORTED) */
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#if defined(SOC_SHA_CRYPTO_DMA) || defined(SOC_AES_CRYPTO_DMA)
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void esp_crypto_dma_lock_acquire(void) {}
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void esp_crypto_dma_lock_release(void) {}
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#endif /* defined(SOC_SHA_CRYPTO_DMA) || defined(SOC_AES_CRYPTO_DMA) */
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#ifdef SOC_MPI_SUPPORTED
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void esp_crypto_mpi_lock_acquire(void) {}
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void esp_crypto_mpi_lock_release(void) {}
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#endif /* SOC_MPI_SUPPORTED */
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#ifdef SOC_ECC_SUPPORTED
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void esp_crypto_ecc_lock_acquire(void) {}
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void esp_crypto_ecc_lock_release(void) {}
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#endif /* SOC_ECC_SUPPORTED */
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#ifdef SOC_ECDSA_SUPPORTED
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void esp_crypto_ecdsa_lock_acquire(void) {}
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void esp_crypto_ecdsa_lock_release(void) {}
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#endif /* SOC_ECDSA_SUPPORTED */
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#if SOC_KEY_MANAGER_SUPPORT_KEY_DEPLOYMENT
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void esp_crypto_key_manager_lock_acquire(void) {}
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void esp_crypto_key_manager_lock_release(void) {}
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#endif /* SOC_KEY_MANAGER_SUPPORT_KEY_DEPLOYMENT */
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#endif /* !NON_OS_BUILD */
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