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https://github.com/espressif/esp-idf.git
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ce27a6e7e0
ECDSA enable pulses a reset that also holds SHA in reset, and SHA shares its DMA with AES. Key Manager enable pulses a reset that also covers the XTS-AES flash encryption key-usage selector. Neither path was serialized against those victims, so a hardware ECDSA/HMAC/DS operation could corrupt a concurrent SHA/AES transfer or an in-flight encrypted flash read. - Take the SHA/AES lock inside esp_crypto_ecdsa_lock_acquire(), before MPI, matching the DS lock order (sha_aes < mpi) - Add esp_crypto_key_mgr_enable_periph_clk_no_reset() and switch ECDSA, HMAC and DS to it; they only need the key-usage selector writable - Hold esp_crypto_key_manager_lock across those clock enable/disable pairs so selector writes stay serialized without resetting KM
148 lines
4.1 KiB
C
148 lines
4.1 KiB
C
/*
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* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include "soc/soc_caps.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef SOC_HMAC_SUPPORTED
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/**
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* @brief Acquire lock for HMAC cryptography peripheral
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*
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* Internally also locks the SHA peripheral, as the HMAC depends on the SHA peripheral
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*/
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void esp_crypto_hmac_lock_acquire(void);
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/**
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* @brief Release lock for HMAC cryptography peripheral
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*
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* Internally also releases the SHA peripheral, as the HMAC depends on the SHA peripheral
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*/
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void esp_crypto_hmac_lock_release(void);
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#endif /* SOC_HMAC_SUPPORTED */
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#ifdef SOC_DIG_SIGN_SUPPORTED
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/**
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* @brief Acquire lock for DS cryptography peripheral
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*
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* Internally also locks the HMAC (which locks SHA), AES and MPI peripheral, as the DS depends on these peripherals
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*/
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void esp_crypto_ds_lock_acquire(void);
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/**
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* @brief Release lock for DS cryptography peripheral
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*
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* Internally also releases the HMAC (which locks SHA), AES and MPI peripheral, as the DS depends on these peripherals
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*/
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void esp_crypto_ds_lock_release(void);
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#endif /* SOC_DIG_SIGN_SUPPORTED */
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#if defined(SOC_SHA_SUPPORTED) || defined(SOC_AES_SUPPORTED)
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/**
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* @brief Acquire lock for the SHA and AES cryptography peripheral.
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*
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*/
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void esp_crypto_sha_aes_lock_acquire(void);
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/**
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* @brief Release lock for the SHA and AES cryptography peripheral.
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*
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*/
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void esp_crypto_sha_aes_lock_release(void);
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#endif /* defined(SOC_SHA_SUPPORTED) || defined(SOC_AES_SUPPORTED) */
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#if defined(SOC_SHA_CRYPTO_DMA) || defined(SOC_AES_CRYPTO_DMA)
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/**
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* This API should be used by all components which use the SHA, AES, HMAC and DS crypto hardware on the ESP32S2.
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* They can not be used in parallel because they use the same DMA or are calling each other.
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* E.g., HMAC uses SHA or DS uses HMAC and AES. See the ESP32S2 Technical Reference Manual for more details.
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*
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* Other unrelated components must not use it.
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*/
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/**
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* Acquire lock for the AES and SHA cryptography peripherals, which both use the crypto DMA.
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*/
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void esp_crypto_dma_lock_acquire(void);
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/**
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* Release lock for the AES and SHA cryptography peripherals, which both use the crypto DMA.
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*/
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void esp_crypto_dma_lock_release(void);
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#endif /* defined(SOC_SHA_CRYPTO_DMA) || defined(SOC_AES_CRYPTO_DMA) */
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#ifdef SOC_MPI_SUPPORTED
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/**
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* @brief Acquire lock for the mpi cryptography peripheral.
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*
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*/
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void esp_crypto_mpi_lock_acquire(void);
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/**
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* @brief Release lock for the mpi/rsa cryptography peripheral.
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*
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*/
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void esp_crypto_mpi_lock_release(void);
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#endif /* SOC_MPI_SUPPORTED */
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#ifdef SOC_ECC_SUPPORTED
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/**
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* @brief Acquire lock for the ECC cryptography peripheral.
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*
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*/
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void esp_crypto_ecc_lock_acquire(void);
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/**
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* @brief Release lock for the ECC cryptography peripheral.
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*
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*/
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void esp_crypto_ecc_lock_release(void);
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#endif /* SOC_ECC_SUPPORTED */
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#ifdef SOC_ECDSA_SUPPORTED
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/**
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* @brief Acquire lock for ECDSA cryptography peripheral
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*
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* Internally also locks the ECC and MPI peripheral, as the ECDSA depends on these peripherals,
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* and the SHA/AES peripheral, because the ECDSA reset holds SHA in reset as well
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*/
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void esp_crypto_ecdsa_lock_acquire(void);
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/**
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* @brief Release lock for ECDSA cryptography peripheral
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*
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* Internally also releases the ECC and MPI peripheral, as the ECDSA depends on these peripherals,
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* and the SHA/AES peripheral, because the ECDSA reset holds SHA in reset as well
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*/
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void esp_crypto_ecdsa_lock_release(void);
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#endif /* SOC_ECDSA_SUPPORTED */
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#if SOC_KEY_MANAGER_SUPPORT_KEY_DEPLOYMENT
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/**
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* @brief Acquire lock for Key Manager peripheral
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*
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* Must be held across esp_crypto_key_mgr_enable_periph_clk(true/false): that
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* helper pulses the Key Manager reset, which also covers the XTS-AES flash
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* encryption key-usage selector on targets that deploy FE keys through KM.
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*/
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void esp_crypto_key_manager_lock_acquire(void);
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/**
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* @brief Release lock for Key Manager peripheral
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*
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* Must be released only after the matching esp_crypto_key_mgr_enable_periph_clk(false).
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*/
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void esp_crypto_key_manager_lock_release(void);
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#endif /* SOC_KEY_MANAGER_SUPPORT_KEY_DEPLOYMENT */
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#ifdef __cplusplus
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}
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#endif
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