mirror of
https://github.com/espressif/esp-idf.git
synced 2026-09-22 13:01:16 +03:00
a671c83b0b
A typical scenario is: when XIP on PSRAM enabled, compiler optimization level is Os. Under certain binary layout, boot hangs and backtrace points to `esp_sleep_config_gpio_isolate`. The root cause is that, during PSRAM initialization, it calls esp_gpio_reserve, which happens to place before the reported function. However, after call, there is no barrier before the clock adjustment in `mspi_timing_enter_low_speed_mode`. The clock gets changed when the cache is still fetching data, resulting in the corrupted data in the end of the cache line. This commits add spi_flash_disable_cache as a barrier to make sure the cache transactions is finished before the clock switch.
PSRAM MSPI Interrupt Handling
Overview
This file (system_layer/esp_psram_mspi.c) handles PSRAM-specific MSPI interrupt registration.
| Chip Type | MSPI_LL_INTR_SHARED |
Behavior |
|---|---|---|
| Shared IRQ | 1 | Register to shared MSPI dispatcher |
| Separate IRQ | 0 | Register standalone PSRAM ISR via esp_intr_alloc() |
Documentation
For detailed architecture, flow diagrams, and API reference, see: