mirror of
https://github.com/espressif/esp-idf.git
synced 2026-10-01 18:50:34 +03:00
Xiao Xufeng
faf6cc4f84
This commit implements a workaround that allows ESP32-C5 to run at 240MHz CPU frequency normally, while automatically reducing CPU frequency during encrypted flash writes to ensure correct operation. The frequency limit is chip revision dependent: - v1.2 and above: limited to 160MHz during encrypted writes - v1.0 and below: limited to 80MHz during encrypted writes Key implementation details: - Frequency limiting is triggered automatically when esp_flash_write_encrypted() is called - Uses start() flags (ESP_FLASH_START_FLAG_LIMIT_CPU_FREQ) to integrate with OS layer - Works with both PM enabled and disabled configurations - Frequency is automatically restored after encrypted write completes - For ESP32-C5 with 120MHz flash, Flash clock and timing registers are adjusted when CPU frequency is reduced to 80MHz - SPI1 timing registers are configured during frequency switching since encrypted writes use SPI1 and must work correctly at reduced CPU frequencies Code improvements: - Use SOC_MSPI_FREQ_AXI_CONSTRAINED capability macro instead of hardcoded chip checks - Control workaround via Kconfig (CONFIG_PM_WORKAROUND_FREQ_LIMIT_ENABLED) instead of hardcoded macros - Add comprehensive test cases covering various PM configurations and edge cases This workaround enables ESP32-C5 applications to benefit from 240MHz CPU performance while maintaining reliable encrypted flash write functionality.
22 lines
740 B
CMake
22 lines
740 B
CMake
idf_build_get_property(target IDF_TARGET)
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set(priv_requires esp_system esp_driver_gpio esp_timer)
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if(${target} STREQUAL "linux")
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return() # This component is not supported by the POSIX/Linux simulator
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endif()
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set(srcs "pm_locks.c" "pm_trace.c" "pm_impl.c")
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if(CONFIG_PM_WORKAROUND_FREQ_LIMIT_ENABLED)
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list(APPEND srcs "pm_c5_flash_freq_limit.c")
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endif()
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if(${target} STREQUAL "esp32c5")
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# pm_c5_flash_freq_limit.c needs spi_flash header when CONFIG_PM_WORKAROUND_FREQ_LIMIT_ENABLED is enabled
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list(APPEND priv_requires spi_flash)
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endif()
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idf_component_register(SRCS ${srcs}
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INCLUDE_DIRS include
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PRIV_REQUIRES "${priv_requires}"
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LDFRAGMENTS linker.lf)
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