gaoxu afe3bfe19f SPI:fix spi slave example sender ccount issue ...

On riscv core, core cycle counter counts the clock cycles only when core is active (not sleeping).
In spi_slave/sender example, it uses ccount (core cycle counter) to do a simple debounce.
Therefore, when using spi_slave/sender and spi_slave/receiver, program will be stuck.
This commit fix this issue by using esp_timer

2022-06-22 15:06:29 +08:00

..

main

SPI:fix spi slave example sender ccount issue

2022-06-22 15:06:29 +08:00

CMakeLists.txt

[examples]: removed hyphens

2021-10-09 13:58:24 +08:00

Makefile

[examples]: removed hyphens

2021-10-09 13:58:24 +08:00