mirror of
https://github.com/espressif/esp-idf.git
synced 2026-10-02 03:00:34 +03:00
Ondrej Kosta
edbf8856ae
Add internal EMAC support for ESP32-S31, including: - HAL/LL layer: emac_ll, emac_hal, emac_clk, emac_periph for S31 - SOC layer: register structs, soc_caps, peripherals linker script, interrupt definitions - MAC driver: clock source configuration via Kconfig, GPIO/DMA adaptations, PHY register defs for clause-45 MDIO - Ethernet examples updated for S31 (basic, build-test-rules, PTP readme) - Refactored existing ESP32/ESP32-P4 EMAC code for shared patterns (emac_clk extraction, struct alignment, periph descriptor cleanup)
62 lines
1.8 KiB
C
62 lines
1.8 KiB
C
/*
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* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "hal/emac_clk.h"
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/* MPLL VCO frequency step for targets that program MPLL from the 40 MHz XTAL (see clk_ll_mpll_set_*). */
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#define EMAC_MPLL_GRID_STEP_HZ (20000000)
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#define EMAC_MPLL_GRID_MAX_STEPS (32)
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/* CPLL grid: f = 40 MHz XTAL * fb_div / ref_div (clk_ll_cpll_*); model fb_div 1..N with ref_div 1 => 40 MHz steps.
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* Max CPLL 320 MHz => N = 8. */
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#define EMAC_CPLL_GRID_STEP_HZ (40000000)
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#define EMAC_CPLL_GRID_MAX_STEPS (8)
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static const emac_clk_info_t emac_clk_cpll = {
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.clk_id = SOC_MOD_CLK_CPLL,
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.step_hz = EMAC_CPLL_GRID_STEP_HZ,
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.max_steps = EMAC_CPLL_GRID_MAX_STEPS,
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.clk_name = "CPLL",
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};
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static const emac_clk_info_t emac_clk_mpll = {
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.clk_id = SOC_MOD_CLK_MPLL,
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.step_hz = EMAC_MPLL_GRID_STEP_HZ,
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.max_steps = EMAC_MPLL_GRID_MAX_STEPS,
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.clk_name = "MPLL",
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};
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static const emac_clk_info_t emac_clk_apll = {
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.clk_id = SOC_MOD_CLK_APLL,
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.step_hz = -1,
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.max_steps = -1,
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.clk_name = "APLL",
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};
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// Order matters! Position can be used to determine the clock source selection
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static const emac_clk_info_t *emac_clk_internal_src[] = {
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&emac_clk_mpll,
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&emac_clk_cpll,
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&emac_clk_apll,
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};
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const emac_clk_internal_info_t emac_clk_internal = {
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.clk_count = sizeof(emac_clk_internal_src) / sizeof(emac_clk_internal_src[0]),
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.clk_src = emac_clk_internal_src,
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};
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// Order matters! Position can be used to determine the clock source selection
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const emac_clk_info_t *emac_clk_phy_ref_src[] = {
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&emac_clk_cpll,
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&emac_clk_mpll,
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};
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const emac_clk_phy_ref_info_t emac_clk_phy_ref = {
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.derived_clk_id = SOC_MOD_CLK_PLL_F50M,
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.clk_count = sizeof(emac_clk_phy_ref_src) / sizeof(emac_clk_phy_ref_src[0]),
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.clk_src = emac_clk_phy_ref_src,
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};
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