mirror of
https://github.com/espressif/esp-idf.git
synced 2026-10-01 10:40:47 +03:00
Nebojsa Cvetkovic
d0ceef20f4
This commit renames all registers in xtensa/specreg.h to by adding the prefix XT_REG_. This is done to avoid naming collisions with similar variable names. A new register file, viz., xt_specreg.h is created. The previous names are still available to use but have been deprecated. Closes https://github.com/espressif/esp-idf/issues/12723 Merges https://github.com/espressif/esp-idf/pull/16040
151 lines
4.7 KiB
C
151 lines
4.7 KiB
C
/*
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* Xtensa Special Register symbolic names
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*/
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/* SPDX-FileCopyrightText: 2005-2011 Tensilica Inc.
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*
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* SPDX-License-Identifier: MIT
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*
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* SPDX-FileContributor: 2025 Espressif Systems (Shanghai) CO LTD
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*/
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/* $Id: //depot/rel/Foxhill/dot.9/Xtensa/OS/include/xtensa/specreg.h#1 $ */
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/*
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* Copyright (c) 2005-2011 Tensilica Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef XTENSA_XT_SPECREG_H
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#define XTENSA_XT_SPECREG_H
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/* Special registers: */
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#define XT_REG_LBEG 0
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#define XT_REG_LEND 1
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#define XT_REG_LCOUNT 2
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#define XT_REG_SAR 3
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#define XT_REG_BR 4
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#define XT_REG_LITBASE 5
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#define XT_REG_SCOMPARE1 12
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#define XT_REG_ACCLO 16
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#define XT_REG_ACCHI 17
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#define XT_REG_MR_0 32
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#define XT_REG_MR_1 33
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#define XT_REG_MR_2 34
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#define XT_REG_MR_3 35
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#define XT_REG_PREFCTL 40
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#define XT_REG_WINDOWBASE 72
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#define XT_REG_WINDOWSTART 73
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#define XT_REG_PTEVADDR 83
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#define XT_REG_RASID 90
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#define XT_REG_ITLBCFG 91
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#define XT_REG_DTLBCFG 92
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#define XT_REG_IBREAKENABLE 96
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#define XT_REG_MEMCTL 97
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#define XT_REG_CACHEATTR 98 /* until T1050, XEA1 */
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#define XT_REG_CACHEADRDIS 98 /* LX7+ */
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#define XT_REG_ATOMCTL 99
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#define XT_REG_DDR 104
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#define XT_REG_MECR 110
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#define XT_REG_IBREAKA_0 128
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#define XT_REG_IBREAKA_1 129
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#define XT_REG_DBREAKA_0 144
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#define XT_REG_DBREAKA_1 145
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#define XT_REG_DBREAKC_0 160
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#define XT_REG_DBREAKC_1 161
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#define XT_REG_CONFIGID0 176
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#define XT_REG_EPC_1 177
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#define XT_REG_EPC_2 178
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#define XT_REG_EPC_3 179
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#define XT_REG_EPC_4 180
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#define XT_REG_EPC_5 181
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#define XT_REG_EPC_6 182
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#define XT_REG_EPC_7 183
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#define XT_REG_DEPC 192
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#define XT_REG_EPS_2 194
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#define XT_REG_EPS_3 195
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#define XT_REG_EPS_4 196
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#define XT_REG_EPS_5 197
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#define XT_REG_EPS_6 198
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#define XT_REG_EPS_7 199
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#define XT_REG_CONFIGID1 208
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#define XT_REG_EXCSAVE_1 209
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#define XT_REG_EXCSAVE_2 210
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#define XT_REG_EXCSAVE_3 211
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#define XT_REG_EXCSAVE_4 212
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#define XT_REG_EXCSAVE_5 213
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#define XT_REG_EXCSAVE_6 214
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#define XT_REG_EXCSAVE_7 215
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#define XT_REG_CPENABLE 224
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#define XT_REG_INTERRUPT 226
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#define XT_REG_INTREAD INTERRUPT /* alternate name for backward compatibility */
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#define XT_REG_INTSET INTERRUPT /* alternate name for backward compatibility */
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#define XT_REG_INTCLEAR 227
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#define XT_REG_INTENABLE 228
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#define XT_REG_PS 230
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#define XT_REG_VECBASE 231
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#define XT_REG_EXCCAUSE 232
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#define XT_REG_DEBUGCAUSE 233
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#define XT_REG_CCOUNT 234
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#define XT_REG_PRID 235
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#define XT_REG_ICOUNT 236
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#define XT_REG_ICOUNTLEVEL 237
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#define XT_REG_EXCVADDR 238
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#define XT_REG_CCOMPARE_0 240
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#define XT_REG_CCOMPARE_1 241
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#define XT_REG_CCOMPARE_2 242
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#define XT_REG_MISC_REG_0 244
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#define XT_REG_MISC_REG_1 245
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#define XT_REG_MISC_REG_2 246
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#define XT_REG_MISC_REG_3 247
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/* Special cases (bases of special register series): */
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#define XT_REG_MR 32
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#define XT_REG_IBREAKA 128
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#define XT_REG_DBREAKA 144
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#define XT_REG_DBREAKC 160
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#define XT_REG_EPC 176
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#define XT_REG_EPS 192
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#define XT_REG_EXCSAVE 208
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#define XT_REG_CCOMPARE 240
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#define XT_REG_MISC_REG 244
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/* Tensilica-defined user registers: */
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#if 0
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/*#define ... 21..24 */ /* (545CK) */
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/*#define ... 140..143 */ /* (545CK) */
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#define XT_REG_EXPSTATE 230 /* Diamond */
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#define XT_REG_THREADPTR 231 /* threadptr option */
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#define XT_REG_FCR 232 /* FPU */
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#define XT_REG_FSR 233 /* FPU */
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#define XT_REG_AE_OVF_SAR 240 /* HiFi2 */
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#define XT_REG_AE_BITHEAD 241 /* HiFi2 */
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#define XT_REG_AE_TS_FTS_BU_BP 242 /* HiFi2 */
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#define XT_REG_AE_SD_NO 243 /* HiFi2 */
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#define XT_REG_VSAR 240 /* VectraLX */
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#define XT_REG_ROUND_LO 242 /* VectraLX */
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#define XT_REG_ROUND_HI 243 /* VectraLX */
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#define XT_REG_CBEGIN 246 /* VectraLX */
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#define XT_REG_CEND 247 /* VectraLX */
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#endif
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#endif /* XTENSA_XT_SPECREG_H */
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