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b697c31f405f989e2966e82c06527dcbf17d8e47
esp-idf/components/riscv
History
Renz Bagaporo 7d75f85221 feat(ulp): build ULP full subprojects as CMake v2 children
2026-07-15 09:14:35 +09:00
..
include
test(ci): re-enable ESP32-H4 in core system test apps
2026-05-13 09:00:12 +08:00
ld
refactor(riscv): added a new API for the interrupts
2024-01-18 16:36:53 +08:00
CMakeLists.txt
feat(ulp): build ULP full subprojects as CMake v2 children
2026-07-15 09:14:35 +09:00
instruction_decode.c
refactor(tools): Tidy up core component files copyright ignore
2024-01-22 18:07:35 +08:00
interrupt_clic.c
fix(riscv): implement a workaround for Zcmp hardware bug
2026-04-10 15:03:09 +08:00
interrupt_intc.c
refactor(riscv): added a new API for the interrupts
2024-01-18 16:36:53 +08:00
interrupt_plic.c
refactor(esp_tee): Revised the secure service ID numbering scheme
2025-01-23 12:39:19 +05:30
interrupt.c
feat(intr): basic interrupt/freertos support for C61
2024-06-12 09:25:47 +08:00
linker.lf
refactor(esp32c61): bus_monitor backward compatible refactor
2025-04-08 22:50:04 +08:00
rv_utils.c
refactor(esp32c61): bus_monitor backward compatible refactor
2025-04-08 22:50:04 +08:00
vectors_clic.S
change(riscv): Remove redundant definition of MEMPROT_ISR
2025-08-04 11:43:01 +05:30
vectors_intc.S
refactor(esp_system): Update all references of the memory protection configs
2025-08-04 11:43:01 +05:30
vectors.S
fix(riscv): implement a workaround for Zcmp hardware bug
2026-04-10 15:03:09 +08:00
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