mirror of
https://github.com/espressif/esp-idf.git
synced 2026-09-22 13:01:16 +03:00
b9ba3ea3ad
1. Added strong function for btdm_compressed_assert.
2. Fixed some berdr hci issues
3. Updated ble config params structure
165 lines
10 KiB
C
165 lines
10 KiB
C
/*
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* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include "btdm_user_cfg.h"
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#include "bredr_user_cfg.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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***************************************************************************************************
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* Local Defined Macros
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***************************************************************************************************
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*/
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#define ESP_BREDR_CTRL_CONFIG_MAGIC_VAL (0x5A5AA5A5)
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#define ESP_BREDR_CTRL_CONFIG_VERSION (0x20260722)
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#if UC_BT_CTRL_BR_EDR_IS_ENABLE
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#define _BT_CTRL_BREDR_INIT_CONFIG_DEFAULT() \
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{ \
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.bredr_version = ESP_BREDR_CTRL_CONFIG_VERSION, \
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.sleep_mode = 0, \
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.bt_test_mode_en = UC_BR_EDR_TEST_MODE_EN, \
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.acl_cca_en = UC_BR_EDR_TX_CCA_EN, \
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.cca_rssi_thr = -UC_BR_EDR_CCA_RSSI_THRESH, \
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.max_acl_conn = UC_BR_EDR_MAX_ACL_CONN, \
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.max_sync_conn = UC_BR_EDR_CTRL_MAX_SYNC_CONN, \
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.cpb_tx_link_num = UC_BR_EDR_CPB_TX_LINK_NB, \
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.cpb_rx_link_num = UC_BR_EDR_CPB_RX_LINK_NB, \
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.bt_sco_datapath = UC_BR_EDR_SCO_DATA_PATH, \
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.hci_tl_type = 0, \
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.hci_tl_funcs = NULL, \
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.cfg_mask = 0, \
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.hw_target_code = 0, \
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.acl_min_tx_pwr = CONFIG_BT_CTRL_BR_EDR_TX_PWR_ACL_MIN, \
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.acl_max_tx_pwr = CONFIG_BT_CTRL_BR_EDR_TX_PWR_ACL_MAX, \
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.apb_tx_pwr = UC_BR_EDR_TX_PWR_APB, \
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.page_tx_pwr = CONFIG_BT_CTRL_BR_EDR_TX_PWR_PAGE, \
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.pscan_tx_pwr = CONFIG_BT_CTRL_BR_EDR_TX_PWR_PSCAN, \
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.iscan_tx_pwr = CONFIG_BT_CTRL_BR_EDR_TX_PWR_ISCAN, \
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.cpb_tx_pwr = UC_BR_EDR_TX_PWR_CPB, \
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.strain_tx_pwr = UC_BR_EDR_TX_PWR_STRAIN, \
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.rf_hw_type = 0, \
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.static_aclu_tx_buf_nb = UC_BR_EDR_ACLU_TX_BUF_NB - UC_BR_EDR_DYNAMIC_ACLU_TX_BUF_NB, \
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.dynamic_aclu_tx_buf_nb = UC_BR_EDR_DYNAMIC_ACLU_TX_BUF_NB, \
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.aclu_rx_buf_nb = UC_BR_EDR_ACLU_RX_BUF_NB, \
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.sync_tx_buf_nb = 0, \
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.sync_rx_buf_nb = 0, \
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.esco_ev4_supp = UC_BR_EDR_ESCO_EV4_SUPP, \
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.esco_ev5_supp = UC_BR_EDR_ESCO_EV5_SUPP, \
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.esco_ev3_2_supp = UC_BR_EDR_ESCO_EV3_2_SUPP, \
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.esco_ev3_3_supp = UC_BR_EDR_ESCO_EV3_3_SUPP, \
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.esco_3_slots_supp = UC_BR_EDR_ESCO_3_SLOTS_SUPP, \
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.bt_legacy_auth_vs_evt = UC_BR_EDR_LEGACY_AUTH_VENDOR_EVT, \
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.inq_filter_en = 0, \
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.dtm_en = 0, \
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.static_sync_tx_buf_nb = UC_BR_EDR_STATIC_SYNC_TX_BUF_NB, \
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.dynamic_sync_tx_buf_nb = UC_BR_EDR_DYNAMIC_SYNC_TX_BUF_NB, \
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.static_sync_rx_buf_nb = UC_BR_EDR_STATIC_SYNC_RX_BUF_NB, \
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.sync_rx_buf_nb_per_link = UC_BR_EDR_SYNC_RX_BUF_NB_PER_LINK, \
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.bredr_magic = ESP_BREDR_CTRL_CONFIG_MAGIC_VAL, \
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}
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#else
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#define _BT_CTRL_BREDR_INIT_CONFIG_DEFAULT() {0}
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#endif // UC_BT_CTRL_BR_EDR_IS_ENABLE
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/*
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***************************************************************************************************
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* Type Definitions
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***************************************************************************************************
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*/
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/**
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* @brief BR/EDR audio data transport path
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*/
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typedef enum {
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ESP_SCO_DATA_PATH_HCI = 0, /*!< data over HCI transport */
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ESP_SCO_DATA_PATH_PCM = 1, /*!< data over PCM interface */
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} esp_sco_data_path_t;
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/**
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* @brief mempool handle type used in BR/EDR controller
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*/
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typedef void *orca_mempool_t;
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/**
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* @brief mempool operations used in BR/EDR controller
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*/
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struct orca_mempool_ops {
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orca_mempool_t (*create_with_pool)(void *mem, size_t pool_bytes,
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size_t max_bytes); /*!< mempool construction */
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void (*destroy)(orca_mempool_t mempool); /*!< mempool destruction */
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void *(*malloc)(orca_mempool_t mempool, size_t size); /*!< allocate memory from mempool */
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void (*free)(orca_mempool_t mempool, void *ptr); /*!< release memory */
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};
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/**
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* @brief BR/EDR controller configuration options
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*/
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typedef struct {
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/*
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* Following parameters can not be configured runtime when call esp_bt_controller_init()
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* They will be overwritten by constant values from menuconfig options or from macros.
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* So, do not modify the value when esp_bt_controller_init()
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*/
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uint32_t bredr_version; /*!< version number of the defined structure */
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/*
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* Following parameters can be configured runtime, when call esp_bt_controller_init()
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*/
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uint8_t sleep_mode; /*!< controller sleep mode */
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uint8_t bt_test_mode_en; /*!< enable br/edr test mode */
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uint8_t acl_cca_en; /*!< Enable BR/EDR ACL Transmit Clear Channel Assessment (TX CCA) */
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int8_t cca_rssi_thr; /*!< BR/EDR RSSI threshold for Transmit Clear Channel Assessment (CCA) */
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uint8_t
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max_acl_conn; /*!< Maximum number of BR/EDR ACL connections. Configurable in menuconfig */
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uint8_t max_sync_conn; /*!< Maximum number of BR/EDR synchronous connections. Configurable in
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menuconfig */
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uint8_t cpb_tx_link_num; /*!< BR/EDR CPB TX link number */
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uint8_t cpb_rx_link_num; /*!< BR/EDR CPB RX link number */
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uint8_t bt_sco_datapath; /*!< SCO data path, i.e. HCI(0) or PCM(1) */
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uint8_t hci_tl_type; /*!< HCI transport layer, UART, VHCI, etc */
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void *hci_tl_funcs; /*!< hci transport functions used, must be set when hci_tl_type is UART */
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uint32_t cfg_mask; /*!< reserved */
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uint32_t hw_target_code; /*!< hardware target */
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int8_t acl_min_tx_pwr; /*!< Default transmit power for ACL minimum */
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int8_t acl_max_tx_pwr; /*!< Default transmit power for ACL maximum */
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int8_t apb_tx_pwr; /*!< Default transmit power for APB */
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int8_t page_tx_pwr; /*!< Default transmit power for Page */
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int8_t pscan_tx_pwr; /*!< Default transmit power for Page Scan */
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int8_t iscan_tx_pwr; /*!< Default transmit power for Inquiry Scan */
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int8_t cpb_tx_pwr; /*!< Default transmit power for CPB TX */
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int8_t strain_tx_pwr; /*!< Default transmit power for Synchronization Train */
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uint8_t rf_hw_type; /*!< RF hardware type */
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uint8_t static_aclu_tx_buf_nb; /*!< Static ACL-U TX buffer number */
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uint8_t dynamic_aclu_tx_buf_nb; /*!< Dynamic ACL-U TX buffer number */
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uint8_t aclu_rx_buf_nb; /*!< ACL-U RX buffer number */
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uint8_t sync_tx_buf_nb; /*!< SCO TX buffer number */
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uint8_t sync_rx_buf_nb; /*!< SCO RX buffer number */
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uint8_t esco_ev4_supp : 1; /*!< eSCO support EV4 packet type */
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uint8_t esco_ev5_supp : 1; /*!< eSCO support EV5 packet type */
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uint8_t esco_ev3_2_supp : 1; /*!< eSCO support 2-EV3 packet type */
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uint8_t esco_ev3_3_supp : 1; /*!< eSCO support 3-EV3 packet type */
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uint8_t esco_3_slots_supp : 1; /*!< eSCO support 2-EV5 and/or 3-EV5 packet type */
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uint8_t bt_legacy_auth_vs_evt
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: 1; /*!< 1 if BR/EDR Legacy Authentication Vendor Specific Event is enabled, which is
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required to protect from BIAS attack; 0 otherwise. Configurable in menuconfig */
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uint8_t inq_filter_en : 1; /*!< Enable inquiry result filter */
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uint8_t dtm_en : 1; /*!< BR/EDR direct test mode */
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uint32_t mempool_size; /*!< Required mempool size used in BR/EDR controller */
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struct orca_mempool_ops *mempool_ops; /*!< mempool operations used in BR/EDR controller */
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uint8_t static_sync_tx_buf_nb; /*!< static sync tx buffers(allocated at init) */
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uint8_t dynamic_sync_tx_buf_nb; /*!< dynamic sync tx buffers(allocated during sync connection establishment) */
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uint8_t static_sync_rx_buf_nb; /*!< total number of static sync rx buffers */
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uint8_t sync_rx_buf_nb_per_link; /*!< sync rx buffers per link (static + dynamic combined) */
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uint32_t bredr_magic; /*!< Magic number */
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} esp_bt_ctrl_bredr_config_t;
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#ifdef __cplusplus
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}
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#endif
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