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9ab7d5eb03
Add ESP32-S31 USB DWC/UTMI LL headers, SoC register structures, peripheral descriptors, capabilities, and linker mappings so the HS OTG controller and UTMI PHY can be built in esp_hal_usb. Introduce SOC_USB_FSLS_PHY_NUM on USB-OTG targets to separate FSLS USB_WRAP support from OTG/UTMI support. Use it to gate usb_wrap, the USB PHY driver, docs, and example build rules on targets without an FSLS PHY. Also add UTMI data pulldown control to the HAL, clear the boot-time DWC suspend state on ESP32-S31, alias the legacy internal PHY target to UTMI for backward compatibility, and extend usb_phy tests for UTMI-only targets.
25 lines
680 B
C
25 lines
680 B
C
/*
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* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stddef.h>
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#include "soc/interrupts.h"
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#include "soc/usb_periph.h"
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/* --------------------------------- Public --------------------------------- */
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const usb_dwc_info_t usb_dwc_info = {
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.controllers = {
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[0] = {
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.fsls_signals = NULL,
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.otg_signals = NULL,
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.internal_phy_io = NULL, // HS PHY is not mapped to any GPIO
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.supported_phys = USB_PHY_INST_UTMI_0,
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.irq = ETS_USB_OTGHS_INTR_SOURCE,
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.irq_2nd_cpu = ETS_USB_OTGHS_ENDP_MULTI_PROC_INTR_SOURCE,
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},
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},
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};
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