Meet Patel d72bdfedc9 fix(ulp): force SW channel control in ULP-RISC-V ADC read ...

On ESP32-S2/S3 the ULP-RISC-V ADC shares the RTC SAR controller with the
main CPU. ulp_adc_init() sets sar1_en_pad_force = 1 so software selects
the channel, but deep-sleep entry resets it to 0 (ULP/HW control). After
that, the per-read channel selection in ulp_riscv_adc_read_channel() is
ignored and every channel returns the same stale value. Single-channel
worked only because the channel never changed.

Re-assert RTC controller (sar1_en_pad_force = 1) before selecting the
channel on each read so multi-channel sampling works after deep sleep.

2026-06-17 21:57:10 +05:30

..

include

refactor(ulp_riscv): Modify ulp i2c read/write functions to return error code

2025-08-20 14:16:44 +05:30

shared/include

feat(ulp): Improved ULP delay API accuracy and removed floating point operations

2026-03-05 10:39:34 +02:00

ulp_core

fix(ulp): force SW channel control in ULP-RISC-V ADC read

2026-06-17 21:57:10 +05:30

ulp_riscv_i2c.c

fix(ulp_riscv): Prioritize error bits over data flags in I2C interrupt wait

2026-06-15 10:13:18 +03:00

ulp_riscv_lock.c

ulp-riscv: added lock API to provide mutual exclusion when sharing variables between the main CPU and the ULP.

2022-08-05 18:16:31 +08:00

ulp_riscv.c

fix(hal): fix the issue of dual-core contention for RTC_CNTL regs

2026-02-10 12:08:03 +08:00