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49fba58f08
riscv_trace_ll_enable_bus_clock and riscv_trace_ll_reset_register operate on shared HP_SYS_CLKRST registers and were called concurrently from both cores during SECONDARY init, creating RMW race conditions. Move the clock/reset logic out of the HAL layer into esp_riscv_trace_early_init, protected by PERIPH_RCC_ATOMIC() spinlock. Wrap the LL functions with macros that enforce the caller must be inside a PERIPH_RCC_ATOMIC() critical section at compile time.
6 lines
197 B
Plaintext
6 lines
197 B
Plaintext
# CONFIG_ESP_TASK_WDT_INIT is not set
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CONFIG_ESP_RISCV_TRACE_ENABLE=y
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CONFIG_ESP_RISCV_TRACE_RESYNC_MODE_PACKET=y
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CONFIG_ESP_RISCV_TRACE_RESYNC_THRESHOLD=32
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CONFIG_ESP_RISCV_TRACE_BUFFER_SIZE=4096
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