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56fa0f2d5b
The LP SPI driver read and wrote the W0..W15 data buffer registers a whole 32-bit word at a time, which overran the caller's buffer for transfers whose length was not a multiple of four bytes and corrupted the received data. Read and write the data buffer byte-granularly so sub-word transfers no longer alias adjacent bytes. The master transfer also programmed the shared bit-length register from tx_length alone, truncating receive-longer-than-transmit transactions, and always enabled MOSI even on read-only transfers, clocking out stale buffer contents. Size each hardware transaction by max(tx_length, rx_length) and gate MOSI/MISO on the corresponding buffer. The slave path reused the master's single-shot flow, so it re-triggered reg_update after preload (clocking out the previous transaction's data) and offered no way for the caller to publish readiness before the master started the clock. Split the slave transfer into an arm step that preloads the buffer and starts the user phase, and a wait step that blocks on TRANS_DONE and drains only the bytes the master actually clocked in, tracked in software since reg_usr is not a reliable busy indicator in slave mode. Set the LP IO direction for the SPI pads, add lp_core_lp_spi_bus_deinit() to release the LP GPIO pins, and reset the LP SPI peripheral at bus initialization so a stale configuration from a previous run cannot leak into the next.