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ae7124abe3
This commit implements a workaround that allows ESP32-C5 to run at 240MHz CPU frequency normally, while automatically reducing CPU frequency during encrypted flash writes to ensure correct operation. The frequency limit is chip revision dependent: - v1.2 and above: limited to 160MHz during encrypted writes - v1.0 and below: limited to 80MHz during encrypted writes Key implementation details: - Frequency limiting is triggered automatically when esp_flash_write_encrypted() is called - Uses start() flags (ESP_FLASH_START_FLAG_LIMIT_CPU_FREQ) to integrate with OS layer - Works with both PM enabled and disabled configurations - Frequency is automatically restored after encrypted write completes - For ESP32-C5 with 120MHz flash, Flash clock and timing registers are adjusted when CPU frequency is reduced to 80MHz - SPI1 timing registers are configured during frequency switching since encrypted writes use SPI1 and must work correctly at reduced CPU frequencies Code improvements: - Use SOC_MSPI_FREQ_AXI_CONSTRAINED capability macro instead of hardcoded chip checks - Control workaround via Kconfig (CONFIG_PM_WORKAROUND_FREQ_LIMIT_ENABLED) instead of hardcoded macros - Add comprehensive test cases covering various PM configurations and edge cases This workaround enables ESP32-C5 applications to benefit from 240MHz CPU performance while maintaining reliable encrypted flash write functionality.
The SoC component
The soc component provides register-level descriptions for targets supported by ESP-IDF.
| File | Description |
|---|---|
xxx_reg.h/xx_struct.h |
Defines registers layout of a specific module. These files are automated, and should not be updated manually. Please note the register names and layout are subject to change between different chip series. |
xxx_pins.h |
Defines the unchangeable GPIOs used by a specific module. e.g. if a high speed signal is routed through IO MUX, its corresponding GPIO is not selectable. |
soc_caps.h |
Describes the differences in capabilities between different chips. The macros here can also affect cmake build system, Kconfig system, docs system, pytest and CI environment. Changes to this file requires extra caution as they are part of the public API. |
xxx_periph.h |
This is the portal for each peripheral module at the SoC layer, containing all relevant register header files and organizing other key information, such as interrupt sources, hardware signal IDs, etc. |
xxx.peripherals.ld |
This is the linker script that defines each module's memory address. |
The SoC Capabilities
soc_caps.h file describes the SoC capabilities. To used the soc capability macros, you should use the macro functions offered by soc/soc_caps_eval.h.
| Macro function | Description | Example |
|---|---|---|
SOC_IS |
Checks if the current SoC is a specific one. | SOC_IS(ESP32) |
SOC_HAS |
Checks if the current SoC has a specific module. | SOC_HAS(DAC) |
SOC_MODULE_ATTR |
Get the attribute of a specific module. | SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL) |
SOC_MODULE_SUPPORT |
Checks if the current SoC supports a specific feature. | SOC_MODULE_SUPPORT(GPTIMER, ETM) |