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- 1. H2 SPI slave DMA transaction length insufficient for CMD_RESET frame - 2. H2 SPI slave BUSY race at boot causing permanent deadlock - 3. H2 INT pin spurious NEGEDGE on chip reset - 4. H2 SPI slave trans_len exceeding buffer size - 5. S3 host RST flag handling preventing Spinel-layer reset detection - 6. S3 stale eventfd events after HardwareReset causing WaitResponse timeout - 7. ot_br missing coprocessor reset failure callback