Jiang Jiang Jian d5ad96e397 Merge branch 'task/v2_aware_component_and_test_gates_v6.1' into 'release/v6.1' ...

fix(components): linux host-build failure fixes+ disable esp_tee in buildv2 + esp_hw_support and xtensa fixes (v6.1)

See merge request espressif/esp-idf!48919

2026-06-05 10:27:29 +08:00

..

baremetal

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deprecated_include

change(xtensa): Deprecate ".../xtensa_timer.h" include path

2023-11-30 21:58:52 +08:00

esp32

fix(gdbstub): xtensa: fix FPU registers read and write

2026-02-02 10:49:16 +07:00

esp32s2

refactor(xtensa): Rename specreg.h register macros

2025-06-17 15:37:33 +02:00

esp32s3

fix(gdbstub): xtensa: fix FPU registers read and write

2026-02-02 10:49:16 +07:00

include

fix(esp32): Fix access to MALLOC_CAP_IRAM_8BIT byte array in loop

2026-02-13 16:12:58 +02:00

test_apps/include

refactor: Remove idf_test component

2026-01-01 02:26:42 +08:00

trax

feat: Update esptool to v5

2025-09-30 15:28:55 +02:00

CMakeLists.txt

fix(xtensa): detect freertos exclusion via __COMPONENT_REQUIRES_COMMON

2026-05-26 13:10:41 +02:00

eri.c

feat(license): Dual-license source files built by OpenOCD stub flasher

2024-01-15 23:45:23 +01:00

linker.lf

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project_include.cmake

fix(xtensa/cmake): do not include project_include.cmake if the architecture is not xtensa

2025-10-30 17:17:49 +08:00

xt_trax.c

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xtensa_context.S

fix(xtensa): Reset zero overhead loop counter in ISRs

2026-03-04 09:09:09 +02:00

xtensa_intr_asm.S

refactor(xtensa): Rename specreg.h register macros

2025-06-17 15:37:33 +02:00

xtensa_intr.c

change(app_trace): move sysview to component registry

2025-11-10 15:55:41 +08:00

xtensa_loadstore_handler.S

fix(esp32): Fix access to MALLOC_CAP_IRAM_8BIT byte array in loop

2026-02-13 16:12:58 +02:00

xtensa_vectors.S

fix(esp_system): update cache livelock workaround bind to interrupt WDT configuration

2026-06-02 17:31:11 +08:00