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https://github.com/espressif/esp-idf.git
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harshal.patil
6dd847c8dd
The digest length and the condition that reserves it at the end of RTC RAM were duplicated in seven places. Hold the reservation in a hidden Kconfig value that is zero when the feature does not apply, so every consumer subtracts it unconditionally, and derive ESP_SECURE_BOOT_DIGEST_LEN from it.
116 lines
5.5 KiB
C
116 lines
5.5 KiB
C
/*
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* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include <stdlib.h>
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#include "esp_attr.h"
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#include "sdkconfig.h"
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#include "soc/soc.h"
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#include "heap_memory_layout.h"
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#include "esp_heap_caps.h"
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#if CONFIG_SECURE_ENABLE_TEE
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#define SRAM_DIRAM_TEE_ORG (SOC_DIRAM_IRAM_LOW)
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#define SRAM_DIRAM_TEE_END (SRAM_DIRAM_TEE_ORG + CONFIG_SECURE_TEE_IRAM_SIZE + CONFIG_SECURE_TEE_DRAM_SIZE)
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#endif
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/**
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* @brief Memory type descriptors. These describe the capabilities of a type of memory in the SoC.
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* Each type of memory map consists of one or more regions in the address space.
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* Each type contains an array of prioritized capabilities.
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* Types with later entries are only taken if earlier ones can't fulfill the memory request.
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*
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* - For a normal malloc (MALLOC_CAP_DEFAULT), give away the DRAM-only memory first, then pass off any dual-use IRAM regions, finally eat into the application memory.
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* - For a malloc where 32-bit-aligned-only access is okay, first allocate IRAM, then DRAM, finally application IRAM.
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* - Application mallocs (PIDx) will allocate IRAM first, if possible, then DRAM.
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* - Most other malloc caps only fit in one region anyway.
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*
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*/
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/* Index of memory in `soc_memory_types[]` */
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enum {
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SOC_MEMORY_TYPE_RAM = 0,
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SOC_MEMORY_TYPE_RTCRAM = 1,
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SOC_MEMORY_TYPE_NUM,
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};
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/* COMMON_CAPS is the set of attributes common to all types of memory on this chip */
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#ifdef CONFIG_ESP_SYSTEM_MEMPROT
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#define ESP32C6_MEM_COMMON_CAPS (MALLOC_CAP_DEFAULT | MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT | MALLOC_CAP_8BIT)
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#else
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#define ESP32C6_MEM_COMMON_CAPS (MALLOC_CAP_DEFAULT | MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT | MALLOC_CAP_8BIT | MALLOC_CAP_EXEC)
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#endif
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/**
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* Defined the attributes and allocation priority of each memory on the chip,
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* The heap allocator will traverse all types of memory types in column High Priority Matching and match the specified caps at first,
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* if no memory caps matched or the allocation is failed, it will go to columns Medium Priority Matching and Low Priority Matching
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* in turn to continue matching.
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*/
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const soc_memory_type_desc_t soc_memory_types[SOC_MEMORY_TYPE_NUM] = {
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/* Mem Type Name High Priority Matching Medium Priority Matching Low Priority Matching */
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[SOC_MEMORY_TYPE_RAM] = { "RAM", { ESP32C6_MEM_COMMON_CAPS | MALLOC_CAP_DMA, 0, 0 }},
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[SOC_MEMORY_TYPE_RTCRAM] = { "RTCRAM", { MALLOC_CAP_RTCRAM, ESP32C6_MEM_COMMON_CAPS, 0 }},
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};
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const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t);
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/**
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* @brief Region descriptors. These describe all regions of memory available, and map them to a type in the above type.
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*
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* @note Because of requirements in the coalescing code which merges adjacent regions,
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* this list should always be sorted from low to high by start address.
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*
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*/
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/**
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* Register the shared buffer area of the last memory block into the heap during heap initialization
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*/
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#define APP_USABLE_DRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE)
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const soc_memory_region_t soc_memory_regions[] = {
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{ 0x40800000, 0x20000, SOC_MEMORY_TYPE_RAM, 0x40800000, false}, //D/IRAM level0, can be used as trace memory
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{ 0x40820000, 0x20000, SOC_MEMORY_TYPE_RAM, 0x40820000, false}, //D/IRAM level1, can be used as trace memory
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{ 0x40840000, 0x20000, SOC_MEMORY_TYPE_RAM, 0x40840000, false}, //D/IRAM level2, can be used as trace memory
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{ 0x40860000, (APP_USABLE_DRAM_END-0x40860000), SOC_MEMORY_TYPE_RAM, 0x40860000, false}, //D/IRAM level3, can be used as trace memory
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{ APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_RAM, APP_USABLE_DRAM_END, true}, //D/IRAM level3, can be used as trace memory (ROM reserved area)
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#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
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{ 0x50000000, (SOC_RTC_DATA_HIGH - SOC_RTC_DATA_LOW), SOC_MEMORY_TYPE_RTCRAM, 0, false}, //LPRAM
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#endif
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};
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const size_t soc_memory_region_count = sizeof(soc_memory_regions) / sizeof(soc_memory_region_t);
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extern int _data_start, _heap_start, _iram_start, _iram_end, _rtc_force_slow_end;
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extern int _rtc_reserved_start, _rtc_reserved_end;
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/**
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* Reserved memory regions.
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* These are removed from the soc_memory_regions array when heaps are created.
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*
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*/
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// Static data region. DRAM used by data+bss and possibly rodata
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SOC_RESERVE_MEMORY_REGION((intptr_t)&_data_start, (intptr_t)&_heap_start, dram_data);
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// Target has a shared D/IRAM virtual address, no need to calculate I_D_OFFSET like previous chips
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SOC_RESERVE_MEMORY_REGION((intptr_t)&_iram_start, (intptr_t)&_iram_end, iram_code);
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/* NOTE: When ESP-TEE is enabled, the start of the internal SRAM
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* is used by the TEE and is protected from any REE access using
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* memory protection mechanisms employed by ESP-TEE.
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*/
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#if CONFIG_SECURE_ENABLE_TEE
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SOC_RESERVE_MEMORY_REGION((intptr_t)SRAM_DIRAM_TEE_ORG, (intptr_t)(SRAM_DIRAM_TEE_END), tee_diram);
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#endif
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#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
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SOC_RESERVE_MEMORY_REGION(SOC_RTC_DRAM_LOW, (intptr_t)&_rtc_force_slow_end, rtcram_data);
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#endif
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SOC_RESERVE_MEMORY_REGION((intptr_t)&_rtc_reserved_start, (intptr_t)&_rtc_reserved_end, rtc_reserved_data);
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