Tiago Medicci cb7b9850c8 fix(ana_cmpr): Fix swapped POS/NEG cross interrupt masks on ESP32-C5/P4/C61 ...

In components/soc/esp32c5/register/soc/gpio_ext_struct.h (ESP32-C5),
components/soc/esp32c61/register/soc/gpio_ext_struct.h (ESP32-C61),
and components/soc/esp32p4/register/hw_ver3/soc/gpio_struct.h
(ESP32-P4), the analog comparator raw/status/enable/clear register
fields are named comp_neg_0_*/comp0_neg_* for bit 0 and
comp_pos_0_*/comp0_pos_* for bit 1, but each field's own comment says
the opposite: bit 0 is documented as "analog comparator pos edge
interrupt raw/status/enable/clear" and bit 1 as the "neg" counterpart.
The LL masks were defined from the field names rather than from this
documented behavior, so ANALOG_CMPR_LL_POS_CROSS_INTR_MASK() ended up
selecting bit 1 and ANALOG_CMPR_LL_NEG_CROSS_INTR_MASK() bit 0.

A new test case, added in the following commit, arms only one cross
direction at a time and checks that a matching transition fires the
callback while the opposite, never-armed direction does not; without
this fix it reproducibly fails on ESP32-C5, ESP32-P4, and ESP32-C61.

Signed-off-by: Tiago Medicci <tiago.medicci@espressif.com>

2026-07-15 14:46:57 -03:00

..

ana_cmpr_ll.h

fix(ana_cmpr): Fix swapped POS/NEG cross interrupt masks on ESP32-C5/P4/C61

2026-07-15 14:46:57 -03:00