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01b86f1269
Both PSRAM layouts were mapped as a single RWX window, so everything in external RAM - the heap included - was executable. PSRAM used as data only is now RW, and under XIP-from-PSRAM it is split per section as ESP32-P4 does: .text RX, .rodata read-only, and the MMU-page alignment gaps and the reclaimed heap RW, so neither is executable. Both describe the layout that esp_psram_init() produces, and the entries are locked, so - again as on ESP32-P4 - they are only narrowed when CONFIG_SPIRAM_PRE_CONFIGURE_MEMORY_PROTECTION says that layout applies. Without it the application owns the region and PSRAM stays RWX. The per-section entries cost one PMP entry more than the 16 available, so the CPU subsystem and peripheral windows are chained as TOR entries, taking one entry instead of three. soc.h is corrected against the S31 bus address map: the peripheral window base was 1 MB too low, and the LP peripheral top, derived from a register base plus a size rather than from the map, was 16 KB short. SOC_NON_CACHEABLE_OFFSET_FLASH is added.
The SoC component
The soc component provides register-level descriptions for targets supported by ESP-IDF.
| File | Description |
|---|---|
xxx_reg.h/xx_struct.h |
Defines registers layout of a specific module. These files are automated, and should not be updated manually. Please note the register names and layout are subject to change between different chip series. |
xxx_pins.h |
Defines the unchangeable GPIOs used by a specific module. e.g. if a high speed signal is routed through IO MUX, its corresponding GPIO is not selectable. |
soc_caps.h |
Describes the differences in capabilities between different chips. The macros here can also affect cmake build system, Kconfig system, docs system, pytest and CI environment. Changes to this file requires extra caution as they are part of the public API. |
xxx_periph.h |
This is the portal for each peripheral module at the SoC layer, containing all relevant register header files and organizing other key information, such as interrupt sources, hardware signal IDs, etc. |
xxx.peripherals.ld |
This is the linker script that defines each module's memory address. |
The SoC Capabilities
soc_caps.h file describes the SoC capabilities. To used the soc capability macros, you should use the macro functions offered by soc/soc_caps_eval.h.
| Macro function | Description | Example |
|---|---|---|
SOC_IS |
Checks if the current SoC is a specific one. | SOC_IS(ESP32) |
SOC_HAS |
Checks if the current SoC has a specific module. | SOC_HAS(DAC) |
SOC_MODULE_ATTR |
Get the attribute of a specific module. | SOC_MODULE_ATTR(GPTIMER, TIMERS_TOTAL) |
SOC_MODULE_SUPPORT |
Checks if the current SoC supports a specific feature. | SOC_MODULE_SUPPORT(GPTIMER, ETM) |