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mirror of https://github.com/espressif/esp-idf.git synced 2026-09-29 09:44:37 +03:00
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8d230c76509fbb7ea07ef2df3cb930ced91fe0a3
esp-idf/components/riscv
T
History
Stefan Stipanovic d0ae774d59 fix(esp_system): enable linking with LLD on RISC-V targets
2026-08-13 21:23:36 +02:00
..
include
test(ci): re-enable ESP32-H4 in core system test apps
2026-05-13 09:00:12 +08:00
ld
…
test_apps
feat(build): add RISC-V ZCMP post-link workaround check
2026-07-22 13:04:20 +07:00
check_zcmp_workaround.cmake
feat(build): add RISC-V ZCMP post-link workaround check
2026-07-22 13:04:20 +07:00
CMakeLists.txt
fix(ulp): clarify buildv2 child marker
2026-07-29 13:08:23 +09:00
hints.yml
feat(build): add RISC-V ZCMP post-link workaround check
2026-07-22 13:04:20 +07:00
instruction_decode.c
…
interrupt_clic.c
fix(riscv): implement a workaround for Zcmp hardware bug
2026-04-10 15:03:09 +08:00
interrupt_intc.c
…
interrupt_plic.c
refactor(esp_tee): Revised the secure service ID numbering scheme
2025-01-23 12:39:19 +05:30
interrupt.c
…
linker.lf
refactor(esp32c61): bus_monitor backward compatible refactor
2025-04-08 22:50:04 +08:00
rv_utils.c
refactor(esp32c61): bus_monitor backward compatible refactor
2025-04-08 22:50:04 +08:00
vectors_clic.S
fix(esp_system): enable linking with LLD on RISC-V targets
2026-08-13 21:23:36 +02:00
vectors_intc.S
refactor(esp_system): Update all references of the memory protection configs
2025-08-04 11:43:01 +05:30
vectors.S
fix(riscv): implement a workaround for Zcmp hardware bug
2026-04-10 15:03:09 +08:00
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