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GCC 16 flags the volatile accumulator in the cache writeback loops even though it is volatile, as it is only used to update itself. Drop the accumulator and rely on the volatile-qualified psram pointer to keep the cache-line reads from being optimized out.
PSRAM MSPI Interrupt Handling
Overview
This file (system_layer/esp_psram_mspi.c) handles PSRAM-specific MSPI interrupt registration.
| Chip Type | MSPI_LL_INTR_SHARED |
Behavior |
|---|---|---|
| Shared IRQ | 1 | Register to shared MSPI dispatcher |
| Separate IRQ | 0 | Register standalone PSRAM ISR via esp_intr_alloc() |
Documentation
For detailed architecture, flow diagrams, and API reference, see: