mirror of
https://github.com/espressif/esp-idf.git
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a7b29bfda9
The Key Manager hardware peripheral in its current form needs further design changes before it can be offered as a production feature. Until a revised peripheral design is available, withdraw ESP-IDF support for it on all Key Manager capable targets.
171 lines
3.9 KiB
C
171 lines
3.9 KiB
C
/*
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* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "soc/soc_caps.h"
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#include "esp_private/esp_crypto_lock_internal.h"
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#include "sdkconfig.h"
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#include "esp_crypto_periph_clk.h"
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#include "esp_crypto_clk.h"
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#if SOC_AES_SUPPORTED
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#include "hal/aes_ll.h"
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#endif
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#if SOC_SHA_SUPPORTED
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#include "hal/sha_ll.h"
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#endif
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#if SOC_MPI_SUPPORTED
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#include "hal/mpi_ll.h"
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#endif
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#if SOC_ECC_SUPPORTED
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#include "hal/ecc_ll.h"
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#endif
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/* NOTE: For ESP32-S2, the HMAC and DS are implemented in the ROM */
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#if SOC_HMAC_SUPPORTED && !CONFIG_IDF_TARGET_ESP32S2
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#include "hal/hmac_ll.h"
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#endif
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#if SOC_DIG_SIGN_SUPPORTED && !CONFIG_IDF_TARGET_ESP32S2
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#include "hal/ds_ll.h"
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#endif
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#if SOC_ECDSA_SUPPORTED
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#include "hal/ecdsa_ll.h"
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#endif
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#if SOC_KEY_MANAGER_SUPPORT_KEY_DEPLOYMENT
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#include "hal/key_mgr_ll.h"
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#endif
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/* Crypto DMA, shared between AES and SHA */
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#if SOC_AES_CRYPTO_DMA && SOC_SHA_CRYPTO_DMA
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#include "hal/crypto_dma_ll.h"
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#endif
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#if NON_OS_BUILD
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// To suppress build errors about spinlock's __DECLARE_RCC_ATOMIC_ENV
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int __DECLARE_RCC_ATOMIC_ENV __attribute__((unused));
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#endif
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#if SOC_AES_SUPPORTED
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void esp_crypto_aes_enable_periph_clk(bool enable)
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{
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AES_RCC_ATOMIC() {
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esp_crypto_common_clk_enable(enable);
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aes_ll_enable_bus_clock(enable);
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if (enable) {
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aes_ll_reset_register();
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}
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#if SOC_AES_CRYPTO_DMA
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crypto_dma_ll_enable_bus_clock(enable);
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if (enable) {
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crypto_dma_ll_reset_register();
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}
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#endif
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}
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}
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#endif
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#if SOC_SHA_SUPPORTED
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void esp_crypto_sha_enable_periph_clk(bool enable)
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{
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SHA_RCC_ATOMIC() {
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esp_crypto_common_clk_enable(enable);
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sha_ll_enable_bus_clock(enable);
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if (enable) {
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sha_ll_reset_register();
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}
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#if SOC_SHA_CRYPTO_DMA
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crypto_dma_ll_enable_bus_clock(enable);
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if (enable) {
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crypto_dma_ll_reset_register();
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}
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#endif
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}
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}
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#endif
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#if SOC_MPI_SUPPORTED
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void esp_crypto_mpi_enable_periph_clk(bool enable)
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{
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MPI_RCC_ATOMIC() {
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esp_crypto_common_clk_enable(enable);
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mpi_ll_enable_bus_clock(enable);
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if (enable) {
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mpi_ll_power_up();
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mpi_ll_reset_register();
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} else {
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mpi_ll_power_down();
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}
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}
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}
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#endif
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#if SOC_ECC_SUPPORTED
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void esp_crypto_ecc_enable_periph_clk(bool enable)
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{
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ECC_RCC_ATOMIC() {
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esp_crypto_common_clk_enable(enable);
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ecc_ll_enable_bus_clock(enable);
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if (enable) {
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ecc_ll_power_up();
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ecc_ll_reset_register();
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} else {
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ecc_ll_power_down();
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}
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}
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}
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#endif
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#if SOC_HMAC_SUPPORTED && !CONFIG_IDF_TARGET_ESP32S2
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void esp_crypto_hmac_enable_periph_clk(bool enable)
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{
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HMAC_RCC_ATOMIC() {
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esp_crypto_common_clk_enable(enable);
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hmac_ll_enable_bus_clock(enable);
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if (enable) {
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hmac_ll_reset_register();
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}
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}
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}
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#endif
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#if SOC_DIG_SIGN_SUPPORTED && !CONFIG_IDF_TARGET_ESP32S2
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void esp_crypto_ds_enable_periph_clk(bool enable)
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{
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DS_RCC_ATOMIC() {
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esp_crypto_common_clk_enable(enable);
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ds_ll_enable_bus_clock(enable);
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if (enable) {
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ds_ll_reset_register();
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}
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}
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}
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#endif
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#if SOC_ECDSA_SUPPORTED
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void esp_crypto_ecdsa_enable_periph_clk(bool enable)
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{
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ECDSA_RCC_ATOMIC() {
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esp_crypto_common_clk_enable(enable);
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ecdsa_ll_enable_bus_clock(enable);
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if (enable) {
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ecdsa_ll_reset_register();
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}
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}
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}
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#endif
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#if SOC_KEY_MANAGER_SUPPORT_KEY_DEPLOYMENT
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void esp_crypto_key_mgr_enable_periph_clk(bool enable)
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{
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KEY_MANAGER_RCC_ATOMIC() {
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esp_crypto_common_clk_enable(enable);
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key_mgr_ll_power_up();
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key_mgr_ll_enable_bus_clock(enable);
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key_mgr_ll_enable_peripheral_clock(enable);
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if (enable) {
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key_mgr_ll_reset_register();
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}
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}
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}
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#endif
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