esp-idf/components/esp_hal_security/test_apps/tee/sdkconfig.defaults.esp32c61 at 752db18455dfec9e307301aec00e24cf99d2e5e2 - esp-idf - chatchai: gitea

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Alexey Lapshin 631ad9033c feat(build): add RISC-V ZCMP post-link workaround check

Validate linked RISC-V executables when
CONFIG_COMPILER_ENABLE_RISCV_ZCMP is enabled on affected chips.
Disassemble each function and reject mstatus.MIE clears that lack an
earlier mintthresh write of 0xff.

Handle csrrci, csrrw, and register-mask csrrc patterns while ignoring
csrrs. Add build-only coverage for valid and invalid sequences with
CMake v1 and v2.

Stop the hardware stack guard before switching stacks during restart,
and keep ZCMP disabled for TEE test apps that still require the
workaround.

2026-07-22 13:04:20 +07:00

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 # Enable SPIRAM
 CONFIG_SPIRAM=y
 # Custom partition table
 CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
 CONFIG_PARTITION_TABLE_CUSTOM=y
 CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv"
 CONFIG_PARTITION_TABLE_FILENAME="partitions.csv"
 # TODO: IDF-14145
 CONFIG_COMPILER_ENABLE_RISCV_ZCMP=n