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510a7f792e
For the dual core chips like ESP32H4 that are running on slow CPU clock frequency (96MHz), the number of events getting dispatched in the test case called "performance test - no dedicated task" were falling short of expectation because of extra overhead with locks etc when runing with a non dedicated task. Even for other chips like ESP32S3, if the main CPU core is running at 80MHz, the result is same. Hence, added a consideration for CPU clock frequency when deciding pass criteria for this test case.
133 lines
5.4 KiB
C
133 lines
5.4 KiB
C
#pragma once
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#include "sdkconfig.h"
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/* put target-specific macros into include/target/idf_performance_target.h */
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#include "idf_performance_target.h"
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/* Define default values in this file with #ifndef if the value could been overwritten in the target-specific headers
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* above. Forgetting this will produce compile-time warnings.
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*/
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#ifndef IDF_PERFORMANCE_MAX_FREERTOS_SPINLOCK_CYCLES_PER_OP
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#define IDF_PERFORMANCE_MAX_FREERTOS_SPINLOCK_CYCLES_PER_OP 215
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#endif
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#ifndef IDF_PERFORMANCE_MAX_FREERTOS_SPINLOCK_CYCLES_PER_OP_PSRAM
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#define IDF_PERFORMANCE_MAX_FREERTOS_SPINLOCK_CYCLES_PER_OP_PSRAM 300
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#endif
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#ifndef IDF_PERFORMANCE_MAX_FREERTOS_SPINLOCK_CYCLES_PER_OP_UNICORE
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#define IDF_PERFORMANCE_MAX_FREERTOS_SPINLOCK_CYCLES_PER_OP_UNICORE 130
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#endif
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#ifndef IDF_PERFORMANCE_MAX_ESP_TIMER_GET_TIME_PER_CALL
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#define IDF_PERFORMANCE_MAX_ESP_TIMER_GET_TIME_PER_CALL 1000
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#endif
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/* Due to code size & linker layout differences interacting with cache, VFS
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microbenchmark currently runs slower with PSRAM enabled. */
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#if !CONFIG_FREERTOS_SMP // IDF-5224
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#ifndef IDF_PERFORMANCE_MAX_VFS_OPEN_WRITE_CLOSE_TIME
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#define IDF_PERFORMANCE_MAX_VFS_OPEN_WRITE_CLOSE_TIME 20000
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#endif
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#ifndef IDF_PERFORMANCE_MAX_VFS_OPEN_WRITE_CLOSE_TIME_PSRAM
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#define IDF_PERFORMANCE_MAX_VFS_OPEN_WRITE_CLOSE_TIME_PSRAM 25000
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#endif
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#else
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#ifndef IDF_PERFORMANCE_MAX_VFS_OPEN_WRITE_CLOSE_TIME
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#define IDF_PERFORMANCE_MAX_VFS_OPEN_WRITE_CLOSE_TIME 62000
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#endif
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#ifndef IDF_PERFORMANCE_MAX_VFS_OPEN_WRITE_CLOSE_TIME_PSRAM
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#define IDF_PERFORMANCE_MAX_VFS_OPEN_WRITE_CLOSE_TIME_PSRAM 66000
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#endif
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#endif
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// throughput performance by iperf
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#ifndef IDF_PERFORMANCE_MIN_TCP_RX_THROUGHPUT
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#define IDF_PERFORMANCE_MIN_TCP_RX_THROUGHPUT 45
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#endif
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#ifndef IDF_PERFORMANCE_MIN_TCP_TX_THROUGHPUT
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#define IDF_PERFORMANCE_MIN_TCP_TX_THROUGHPUT 40
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#endif
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#ifndef IDF_PERFORMANCE_MIN_UDP_RX_THROUGHPUT
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#define IDF_PERFORMANCE_MIN_UDP_RX_THROUGHPUT 64
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#endif
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#ifndef IDF_PERFORMANCE_MIN_UDP_TX_THROUGHPUT
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#define IDF_PERFORMANCE_MIN_UDP_TX_THROUGHPUT 50
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#endif
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// throughput performance by ethernet iperf
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#ifndef IDF_PERFORMANCE_MIN_TCP_RX_ETH_THROUGHPUT
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#define IDF_PERFORMANCE_MIN_TCP_RX_ETH_THROUGHPUT 20
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#endif
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#ifndef IDF_PERFORMANCE_MIN_TCP_TX_ETH_THROUGHPUT
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#define IDF_PERFORMANCE_MIN_TCP_TX_ETH_THROUGHPUT 30
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#endif
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#ifndef IDF_PERFORMANCE_MIN_UDP_RX_ETH_THROUGHPUT
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#define IDF_PERFORMANCE_MIN_UDP_RX_ETH_THROUGHPUT 50
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#endif
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#ifndef IDF_PERFORMANCE_MIN_UDP_TX_ETH_THROUGHPUT
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#define IDF_PERFORMANCE_MIN_UDP_TX_ETH_THROUGHPUT 70
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#endif
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#ifndef IDF_PERFORMANCE_MIN_TCP_RX_ETH_THROUGHPUT_SPI_ETH
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#define IDF_PERFORMANCE_MIN_TCP_RX_ETH_THROUGHPUT_SPI_ETH 6
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#endif
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#ifndef IDF_PERFORMANCE_MIN_TCP_TX_ETH_THROUGHPUT_SPI_ETH
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#define IDF_PERFORMANCE_MIN_TCP_TX_ETH_THROUGHPUT_SPI_ETH 8
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#endif
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#ifndef IDF_PERFORMANCE_MIN_UDP_RX_ETH_THROUGHPUT_SPI_ETH
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#define IDF_PERFORMANCE_MIN_UDP_RX_ETH_THROUGHPUT_SPI_ETH 8
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#endif
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#ifndef IDF_PERFORMANCE_MIN_UDP_TX_ETH_THROUGHPUT_SPI_ETH
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#define IDF_PERFORMANCE_MIN_UDP_TX_ETH_THROUGHPUT_SPI_ETH 10
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#endif
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// events dispatched per second by event loop library
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#if !CONFIG_FREERTOS_SMP // IDF-5112
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#if CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ < 100 // Allowing lesser event dispatch performance for slower CPU frequency chips
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#ifndef IDF_PERFORMANCE_MIN_EVENT_DISPATCH
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#define IDF_PERFORMANCE_MIN_EVENT_DISPATCH 11000
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#endif
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#ifndef IDF_PERFORMANCE_MIN_EVENT_DISPATCH_PSRAM
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#define IDF_PERFORMANCE_MIN_EVENT_DISPATCH_PSRAM 9000
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#endif
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#else
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#ifndef IDF_PERFORMANCE_MIN_EVENT_DISPATCH
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#define IDF_PERFORMANCE_MIN_EVENT_DISPATCH 25000
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#endif
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#ifndef IDF_PERFORMANCE_MIN_EVENT_DISPATCH_PSRAM
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#define IDF_PERFORMANCE_MIN_EVENT_DISPATCH_PSRAM 21000
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#endif
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#endif
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#else
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#ifndef IDF_PERFORMANCE_MIN_EVENT_DISPATCH
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#define IDF_PERFORMANCE_MIN_EVENT_DISPATCH 18000
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#endif
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#ifndef IDF_PERFORMANCE_MIN_EVENT_DISPATCH_PSRAM
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#define IDF_PERFORMANCE_MIN_EVENT_DISPATCH_PSRAM 14000
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#endif
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#endif
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#ifndef IDF_PERFORMANCE_MAX_SPILL_REG_CYCLES
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#define IDF_PERFORMANCE_MAX_SPILL_REG_CYCLES 150
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#endif
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#ifndef IDF_PERFORMANCE_MAX_ISR_ENTER_CYCLES
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#define IDF_PERFORMANCE_MAX_ISR_ENTER_CYCLES 290
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#endif
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#ifndef IDF_PERFORMANCE_MAX_ISR_EXIT_CYCLES
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#define IDF_PERFORMANCE_MAX_ISR_EXIT_CYCLES 565
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#endif
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//time to perform the task selection plus context switch (from task)
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#ifndef IDF_PERFORMANCE_MAX_SCHEDULING_TIME
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#define IDF_PERFORMANCE_MAX_SCHEDULING_TIME 2000
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#endif
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#ifndef IDF_PERFORMANCE_MAX_MALLOC_DEFAULT_AVERAGE_TIME
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#define IDF_PERFORMANCE_MAX_MALLOC_DEFAULT_AVERAGE_TIME 2600
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#endif
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#ifndef IDF_PERFORMANCE_MAX_FREE_DEFAULT_AVERAGE_TIME
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#define IDF_PERFORMANCE_MAX_FREE_DEFAULT_AVERAGE_TIME 950
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#endif
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