mirror of
https://github.com/espressif/esp-idf.git
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f386b718e1
spi_flash_mmap_page_num_init() passed a literal 128 while the ROM searches Cache_Get_DROM_MMU_End() / 4 entries -- 256 on esp32c5, c6, h2 and s3 -- so its free-page scan ran off the array and judged entries from stale heap bytes. The refcount bump on the commit path indexes the same way, so a mapping placed above entry 127 also writes past the array and corrupts the heap behind it. esp32c61 and esp32h21 have the ROM mmap but never program the size and have no soc/mmu.h to read it from, so they keep 128.
344 lines
9.7 KiB
C
344 lines
9.7 KiB
C
/*
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* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdlib.h>
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#include <assert.h>
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#include <string.h>
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#include <stdio.h>
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#include <sys/param.h> // For MIN/MAX(a, b)
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#include <soc/soc.h>
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#include <soc/soc_memory_layout.h>
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#include "soc/io_mux_reg.h"
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#include "soc/spi_pins.h"
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#include "sdkconfig.h"
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#include "esp_attr.h"
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#include "esp_cpu.h"
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#include "esp_log.h"
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#include "esp_private/system_internal.h"
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#include "esp_private/startup_internal.h"
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#include "esp_private/spi_flash_os.h"
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#include "esp_private/esp_clk.h"
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#include "esp_private/esp_gpio_reserve.h"
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#if CONFIG_IDF_TARGET_ESP32
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#include "esp32/rom/cache.h"
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#include "esp32/rom/spi_flash.h"
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#elif CONFIG_IDF_TARGET_ESP32S2
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#include "esp32s2/rom/cache.h"
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#elif CONFIG_IDF_TARGET_ESP32S3
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#include "soc/spi_mem_reg.h"
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#include "esp32s3/rom/opi_flash.h"
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#include "esp32s3/rom/cache.h"
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#include "esp_private/opi_flash_private.h"
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#elif CONFIG_IDF_TARGET_ESP32C3
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#include "esp32c3/rom/cache.h"
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#elif CONFIG_IDF_TARGET_ESP32C2
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#include "esp32c2/rom/cache.h"
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#elif CONFIG_IDF_TARGET_ESP32C6
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#include "esp32c6/rom/cache.h"
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#elif CONFIG_IDF_TARGET_ESP32C61
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#include "esp32c61/rom/cache.h"
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#endif
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#include "esp_rom_spiflash.h"
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#include "esp_private/mspi_timing_tuning.h"
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#include "esp_private/cache_utils.h"
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#include "esp_attr.h"
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#include "bootloader_flash.h"
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#include "bootloader_flash_config.h"
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#include "esp_compiler.h"
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#include "esp_rom_efuse.h"
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#include "esp_rom_caps.h"
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#include "soc/chip_revision.h"
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#include "hal/efuse_hal.h"
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#if CONFIG_SPIRAM
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#include "esp_private/esp_psram_io.h"
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#endif
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#if SOC_MEMSPI_CLOCK_IS_INDEPENDENT
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#include "hal/cache_hal.h"
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#endif
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/* bytes erased by SPIEraseBlock() ROM function */
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#define BLOCK_ERASE_SIZE 65536
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/* Limit number of bytes written/read in a single SPI operation,
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as these operations disable all higher priority tasks from running.
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*/
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#ifdef CONFIG_SPI_FLASH_WRITE_CHUNK_SIZE
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#define MAX_WRITE_CHUNK CONFIG_SPI_FLASH_WRITE_CHUNK_SIZE
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#else
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#define MAX_WRITE_CHUNK 8192
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#endif // CONFIG_SPI_FLASH_WRITE_CHUNK_SIZE
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#define MAX_READ_CHUNK 16384
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static const char *TAG __attribute__((unused)) = "spi_flash";
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const DRAM_ATTR spi_flash_guard_funcs_t g_flash_guard_default_ops = {
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.start = spi_flash_disable_interrupts_caches_and_other_cpu,
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.end = spi_flash_enable_interrupts_caches_and_other_cpu,
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};
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const DRAM_ATTR spi_flash_guard_funcs_t g_flash_guard_no_os_ops = {
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.start = spi_flash_disable_interrupts_caches_and_other_cpu_no_os,
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.end = spi_flash_enable_interrupts_caches_no_os,
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};
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static const spi_flash_guard_funcs_t *s_flash_guard_ops;
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void IRAM_ATTR spi_flash_guard_set(const spi_flash_guard_funcs_t *funcs)
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{
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s_flash_guard_ops = funcs;
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}
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const spi_flash_guard_funcs_t *IRAM_ATTR spi_flash_guard_get(void)
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{
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return s_flash_guard_ops;
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}
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#if CONFIG_SPI_FLASH_ROM_IMPL
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#include "esp_heap_caps.h"
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#if ESP_ROM_HAS_SPI_FLASH_MMAP
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#if ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE
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#include "soc/mmu.h"
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#define ROM_MMAP_PAGE_NUM (CACHE_DROM_MMU_MAX_END / sizeof(uint32_t))
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#else
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#define ROM_MMAP_PAGE_NUM 128
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#endif
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#endif
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void IRAM_ATTR *spi_flash_malloc_internal(size_t size)
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{
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return heap_caps_malloc(size, MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL);
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}
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void IRAM_ATTR spi_flash_rom_impl_init(void)
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{
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spi_flash_guard_set(&g_flash_guard_default_ops);
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#if ESP_ROM_HAS_SPI_FLASH_MMAP
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/* These two functions are in ROM only */
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extern void spi_flash_mmap_os_func_set(void *(*func1)(size_t size), void (*func2)(void *p));
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spi_flash_mmap_os_func_set(spi_flash_malloc_internal, heap_caps_free);
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extern esp_err_t spi_flash_mmap_page_num_init(uint32_t page_num);
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spi_flash_mmap_page_num_init(ROM_MMAP_PAGE_NUM);
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#endif // ESP_ROM_HAS_SPI_FLASH_MMAP
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}
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#endif
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bool IRAM_ATTR spi_flash_is_octal_mode_enabled(void)
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{
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#if SOC_SPI_MEM_SUPPORT_FLASH_OPI_MODE
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return efuse_ll_get_flash_type();
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#else
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return false;
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#endif
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}
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void IRAM_ATTR esp_mspi_pin_init(void)
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{
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#if SOC_SPI_MEM_SUPPORT_FLASH_OPI_MODE
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bool octal_mspi_required = spi_flash_is_octal_mode_enabled();
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#if CONFIG_SPIRAM_MODE_OCT
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octal_mspi_required |= true;
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#endif
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if (octal_mspi_required) {
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esp_rom_opiflash_pin_config();
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mspi_timing_set_pin_drive_strength();
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}
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//Set F4R4 board pin drive strength. TODO: IDF-3663
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#endif
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}
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void esp_mspi_pin_reserve(void)
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{
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uint64_t reserve_pin_mask = 0;
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uint8_t mspi_io;
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for (esp_mspi_io_t i = 0; i < ESP_MSPI_IO_MAX; i++) {
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#if SOC_SPI_MEM_SUPPORT_FLASH_OPI_MODE
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if (!spi_flash_is_octal_mode_enabled()
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&& i >= ESP_MSPI_IO_DQS && i <= ESP_MSPI_IO_D7) {
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continue;
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}
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#endif
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mspi_io = esp_mspi_get_io(i);
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if (mspi_io < 64) { // 'reserve_pin_mask' have 64 bits length
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reserve_pin_mask |= BIT64(mspi_io);
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}
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}
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esp_gpio_reserve(reserve_pin_mask);
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}
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esp_err_t IRAM_ATTR spi_flash_init_chip_state(void)
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{
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#if SOC_SPI_MEM_SUPPORT_FLASH_OPI_MODE
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if (spi_flash_is_octal_mode_enabled()) {
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return esp_opiflash_init(rom_spiflash_legacy_data->chip.device_id);
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}
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#endif
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#if CONFIG_SPI_FLASH_HPM_ON
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return spi_flash_enable_high_performance_mode();
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#endif // CONFIG_SPI_FLASH_HPM_ON
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return ESP_OK;
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}
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void IRAM_ATTR spi_flash_set_rom_required_regs(void)
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{
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#if SOC_SPI_MEM_SUPPORT_FLASH_OPI_MODE
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if (spi_flash_is_octal_mode_enabled()) {
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//Disable the variable dummy mode when doing timing tuning
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CLEAR_PERI_REG_MASK(SPI_MEM_DDR_REG(1), SPI_MEM_SPI_FMEM_VAR_DUMMY);
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/**
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* STR /DTR mode setting is done every time when `esp_rom_opiflash_exec_cmd` is called
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*
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* Add any registers that are not set in ROM SPI flash functions here in the future
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*/
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}
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#endif
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}
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static const uint8_t s_mspi_io_num_default[] = {
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MSPI_IOMUX_PIN_NUM_CLK,
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MSPI_IOMUX_PIN_NUM_MISO,
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MSPI_IOMUX_PIN_NUM_MOSI,
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MSPI_IOMUX_PIN_NUM_CS0,
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MSPI_IOMUX_PIN_NUM_HD,
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MSPI_IOMUX_PIN_NUM_WP,
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#if SOC_SPI_MEM_SUPPORT_FLASH_OPI_MODE
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MSPI_IOMUX_PIN_NUM_DQS,
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MSPI_IOMUX_PIN_NUM_D4,
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MSPI_IOMUX_PIN_NUM_D5,
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MSPI_IOMUX_PIN_NUM_D6,
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MSPI_IOMUX_PIN_NUM_D7
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#endif // SOC_SPI_MEM_SUPPORT_FLASH_OPI_MODE
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};
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uint8_t esp_mspi_get_io(esp_mspi_io_t io)
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{
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#if CONFIG_SPIRAM
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if (io == ESP_MSPI_IO_CS1) {
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return esp_psram_io_get_cs_io();
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}
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#endif
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assert(io >= ESP_MSPI_IO_CLK);
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#if SOC_SPI_MEM_SUPPORT_FLASH_OPI_MODE
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assert(io <= ESP_MSPI_IO_D7);
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#else
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assert(io <= ESP_MSPI_IO_WP);
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#endif
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#if SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE
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uint8_t mspi_io = 0;
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uint32_t spiconfig = 0;
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if (io == ESP_MSPI_IO_WP) {
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/**
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* wp pad is a bit special:
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* 1. since 32's efuse does not have enough bits for wp pad, so wp pad config put in flash bin header
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* 2. rom code take 0x3f as invalid wp pad num, but take 0 as other invalid mspi pads num
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*/
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#if CONFIG_IDF_TARGET_ESP32
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return bootloader_flash_get_wp_pin();
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#else
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spiconfig = esp_rom_efuse_get_flash_wp_gpio();
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return (spiconfig == 0x3f) ? s_mspi_io_num_default[io] : spiconfig & 0x3f;
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#endif
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}
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#if SOC_SPI_MEM_SUPPORT_FLASH_OPI_MODE
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spiconfig = (io < ESP_MSPI_IO_WP) ? esp_rom_efuse_get_flash_gpio_info() : esp_rom_efuse_get_opiconfig();
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#else
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spiconfig = esp_rom_efuse_get_flash_gpio_info();
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#endif // SOC_SPI_MEM_SUPPORT_FLASH_OPI_MODE
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if (spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_SPI) {
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mspi_io = s_mspi_io_num_default[io];
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} else if (io < ESP_MSPI_IO_WP) {
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/**
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* [0 : 5] -- CLK
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* [6 :11] -- Q(D1)
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* [12:17] -- D(D0)
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* [18:23] -- CS
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* [24:29] -- HD(D3)
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*/
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mspi_io = (spiconfig >> io * 6) & 0x3f;
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}
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#if SOC_SPI_MEM_SUPPORT_FLASH_OPI_MODE
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else {
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/**
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* [0 : 5] -- DQS
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* [6 :11] -- D4
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* [12:17] -- D5
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* [18:23] -- D6
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* [24:29] -- D7
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*/
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mspi_io = (spiconfig >> (io - ESP_MSPI_IO_DQS) * 6) & 0x3f;
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}
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#endif // SOC_SPI_MEM_SUPPORT_FLASH_OPI_MODE
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return mspi_io;
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#else // SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE
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return s_mspi_io_num_default[io];
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#endif // SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE
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}
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#if !CONFIG_IDF_TARGET_ESP32P4 || !CONFIG_APP_BUILD_TYPE_RAM // IDF-10019
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esp_err_t IRAM_ATTR esp_mspi_32bit_address_flash_feature_check(void)
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{
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#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2
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ESP_EARLY_LOGE(TAG, "32bit address (flash over 16MB) has high risk on this chip");
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return ESP_ERR_NOT_SUPPORTED;
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#elif CONFIG_IDF_TARGET_ESP32P4
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// IDF-10019
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unsigned chip_version = efuse_hal_chip_revision();
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if (unlikely(!ESP_CHIP_REV_ABOVE(chip_version, 1))) {
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ESP_EARLY_LOGE(TAG, "32bit address (flash over 16MB) has high risk on ESP32P4 v0.0");
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return ESP_ERR_NOT_SUPPORTED;
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}
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#endif
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return ESP_OK;
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}
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#endif // !CONFIG_IDF_TARGET_ESP32P4 || !CONFIG_APP_BUILD_TYPE_RAM
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#if CONFIG_ESP_SLEEP_SET_FLASH_DPD
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static esp_err_t dpd_enter_func(void)
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{
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spi_flash_ll_enter_dpd(&SPIMEM_LL_APB);
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while (!spi_flash_ll_cmd_is_done(&SPIMEM_LL_APB)) {
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//nop
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}
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return ESP_OK;
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}
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static esp_err_t dpd_exit_func(void)
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{
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spi_flash_ll_exit_dpd(&SPIMEM_LL_APB);
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while (!spi_flash_ll_cmd_is_done(&SPIMEM_LL_APB)) {
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//nop
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}
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return ESP_OK;
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}
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ESP_SYSTEM_INIT_FN(init_flash_dpd, CORE, BIT(0), 125)
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{
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// Register DPD function pointers
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static spi_flash_dpd_funcs_t dpd_funcs = {
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.enter_dpd = dpd_enter_func,
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.exit_dpd = dpd_exit_func,
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};
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spi_flash_dpd_register_funcs(&dpd_funcs);
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return ESP_OK;
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}
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#endif // CONFIG_ESP_SLEEP_SET_FLASH_DPD
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void esp_mspi_flash_ops_include_func(void)
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{
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// Linker hook function, exists to make the linker examine this file so that
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// the init_flash_dpd ESP_SYSTEM_INIT_FN above is not discarded.
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}
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