mirror of
https://github.com/espressif/esp-idf.git
synced 2026-07-19 17:33:19 +03:00
e3570108ac
Default timeout for interrupt WDT was increased by default on ESP32, due to some heap integrity check APIs taking a long time on large PSRAMs and causing timeouts. But this adjustment was only done for ESP32, not later chips, even though they may experience the same issue. Adjusted to have the same behavior on all chips with PSRAM enabled, making it consistant with the docs. Closes https://github.com/espressif/esp-idf/issues/18360
516 lines
22 KiB
Plaintext
516 lines
22 KiB
Plaintext
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menu "ESP System Settings"
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# Insert chip-specific cpu config
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rsource "./port/soc/$IDF_TARGET/Kconfig.cpu"
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orsource "./port/soc/$IDF_TARGET/Kconfig.cache"
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orsource "./port/soc/$IDF_TARGET/Kconfig.memory"
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orsource "./port/soc/$IDF_TARGET/Kconfig.tracemem"
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config ESP_SYSTEM_IN_IRAM
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bool "Place system functions in IRAM" if SPI_FLASH_AUTO_SUSPEND
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default y
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help
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The following system functions will be placed in IRAM if this option is enabled:
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- system startup
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- system time
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- system error
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- system restart
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- system crosscore
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- system debug
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- system APB backup DMA lock
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- system application tick hook
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- Unified Behavior Sanitizer (UBSAN) hook
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- Interrupt watchdog handler
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- XTAL32K watchdog timer
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- IPC and IPC ISR
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choice ESP_SYSTEM_PANIC
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prompt "Panic handler behaviour"
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default ESP_SYSTEM_PANIC_PRINT_REBOOT
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help
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If FreeRTOS detects unexpected behaviour or an unhandled exception, the panic handler is
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invoked. Configure the panic handler's action here.
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config ESP_SYSTEM_PANIC_PRINT_HALT
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bool "Print registers and halt"
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depends on !ESP_SYSTEM_GDBSTUB_RUNTIME
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help
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Outputs the relevant registers over the serial port and halt the
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processor. Needs a manual reset to restart.
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config ESP_SYSTEM_PANIC_PRINT_REBOOT
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bool "Print registers and reboot"
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depends on !ESP_SYSTEM_GDBSTUB_RUNTIME
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help
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Outputs the relevant registers over the serial port and immediately
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reset the processor.
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config ESP_SYSTEM_PANIC_SILENT_REBOOT
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bool "Silent reboot"
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depends on !ESP_SYSTEM_GDBSTUB_RUNTIME
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help
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Just resets the processor without outputting anything
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config ESP_SYSTEM_PANIC_GDBSTUB
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bool "GDBStub on panic"
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depends on ESP_GDBSTUB_ENABLED
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help
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Invoke gdbstub on the serial port, allowing for gdb to attach to it to do a postmortem
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of the crash.
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endchoice
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config ESP_SYSTEM_PANIC_REBOOT_DELAY_SECONDS
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int "Panic reboot delay (Seconds)"
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default 0
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range 0 99
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depends on ESP_SYSTEM_PANIC_PRINT_REBOOT
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help
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After the panic handler executes, you can specify a number of seconds to
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wait before the device reboots.
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config ESP_SYSTEM_SINGLE_CORE_MODE
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bool
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default y if IDF_TARGET_LINUX
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default n
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help
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Only initialize and use the main core.
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config ESP_SYSTEM_RTC_EXT_XTAL
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# This is a High Layer Kconfig option, invisible, can be selected by other Kconfig option
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# e.g. It will be selected on when RTC_CLK_SRC_EXT_CRYS is on
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bool
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default n
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config ESP_SYSTEM_RTC_EXT_OSC
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# This is a High Layer Kconfig option, invisible, can be selected by other Kconfig option
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# e.g. It will be selected on when ESPX_RTC_CLK_SRC_EXT_OSC is on
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bool
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default n
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config ESP_SYSTEM_RTC_EXT_XTAL_BOOTSTRAP_CYCLES
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int "Bootstrap cycles for external 32kHz crystal"
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depends on ESP_SYSTEM_RTC_EXT_XTAL
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default 5 if IDF_TARGET_ESP32
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default 0
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range 0 32768
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help
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To reduce the startup time of an external RTC crystal,
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we bootstrap it with a 32kHz square wave for a fixed number of cycles.
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Setting 0 will disable bootstrapping (if disabled, the crystal may take
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longer to start up or fail to oscillate under some conditions).
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If this value is too high, a faulty crystal may initially start and then fail.
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If this value is too low, an otherwise good crystal may not start.
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To accurately determine if the crystal has started,
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set a larger "Number of cycles for RTC_SLOW_CLK calibration" (about 3000).
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config ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK
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bool
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default n if IDF_TARGET_ESP32 && !ESP_SYSTEM_SINGLE_CORE_MODE
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default y
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depends on SOC_RTC_FAST_MEM_SUPPORTED
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config ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
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bool "Enable RTC fast memory for dynamic allocations"
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default y
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depends on ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK
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help
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This config option allows to add RTC fast memory region to system heap with capability
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similar to that of DRAM region but without DMA. Speed wise RTC fast memory operates on
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APB clock and hence does not have much performance impact.
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choice ESP_BACKTRACING_METHOD
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prompt "Backtracing method"
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default ESP_SYSTEM_NO_BACKTRACE
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depends on IDF_TARGET_ARCH_RISCV
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help
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Configure how backtracing will be performed at runtime when a panic occurs.
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config ESP_SYSTEM_NO_BACKTRACE
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bool "No backtracing"
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help
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When selected, no backtracing will be performed at runtime. By using idf.py monitor, it
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is still possible to get a backtrace when a panic occurs.
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config ESP_SYSTEM_USE_EH_FRAME
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bool "Generate and use eh_frame for backtracing"
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help
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Generate DWARF information for each function of the project. These information will parsed and used to
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perform backtracing when panics occur. Activating this option will activate asynchronous frame
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unwinding and generation of both .eh_frame and .eh_frame_hdr sections, resulting in a bigger binary
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size (20% to 100% larger). The main purpose of this option is to be able to have a backtrace parsed
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and printed by the program itself, regardless of the serial monitor used.
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This option is not recommended to be used for production.
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config ESP_SYSTEM_USE_FRAME_POINTER
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bool "Use CPU Frame Pointer register"
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help
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This configuration allows the compiler to allocate CPU register s0 as the frame pointer. The main usage
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of the frame pointer is to be able to generate a backtrace from the panic handler on exception.
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Enabling this option results in bigger and slightly slower code since all functions will have
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to populate this register and won't be able to use it as a general-purpose register anymore.
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endchoice
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config ESP_SYSTEM_MEMPROT
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bool "Enable memory protection"
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default y
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depends on SOC_CPU_IDRAM_SPLIT_USING_PMP || SECURE_ENABLE_TEE || SOC_MEMPROT_SUPPORTED
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help
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This option enables memory protection for the valid memory regions.
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This feature also automatically splits the ROM, RAM and flash memory into data and
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instruction segments and sets Read/Execute permissions for the instruction part
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(below given splitting address) and Read/Write permissions for the data part
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(above the splitting address). The memory protection is effective on all access
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through the IRAM0 and DRAM0 buses.
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Note: allocating memory with MALLOC_CAP_EXEC capability is not possible when this config is enabled.
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choice ESP_SYSTEM_MEMPROT_MODE
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prompt "Memory Protection configurations"
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depends on ESP_SYSTEM_MEMPROT
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default ESP_SYSTEM_MEMPROT_TEE if SECURE_ENABLE_TEE
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default ESP_SYSTEM_MEMPROT_PMP if SOC_CPU_IDRAM_SPLIT_USING_PMP && !SECURE_ENABLE_TEE
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default ESP_SYSTEM_MEMPROT_PMS if SOC_MEMPROT_SUPPORTED
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config ESP_SYSTEM_MEMPROT_PMS
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bool "Enable Permission Control Module (PMS) configurations"
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depends on SOC_MEMPROT_SUPPORTED
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help
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This option enables memory protection using the Permission Control Module (PMS).
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config ESP_SYSTEM_MEMPROT_PMP
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bool "Enable CPU's Physical Memory Protection (PMP) configurations"
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depends on SOC_CPU_IDRAM_SPLIT_USING_PMP && !SECURE_ENABLE_TEE
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help
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This option enables memory protection using CPU PMP.
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config ESP_SYSTEM_MEMPROT_TEE
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bool "Enable Trusted Execution Environment (TEE) configurations"
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depends on SECURE_ENABLE_TEE
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help
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This option enables the default memory protection provided by TEE.
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endchoice
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config ESP_SYSTEM_MEMPROT_PMS_LOCK
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bool "Lock memory protection settings"
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depends on ESP_SYSTEM_MEMPROT && ESP_SYSTEM_MEMPROT_PMS
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default y
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help
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Once locked, memory protection settings cannot be changed anymore.
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The lock is reset only on the chip startup.
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config ESP_SYSTEM_MEMPROT_PMP_LP_CORE_RESERVE_MEM_EXEC
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bool "Make LP core reserved memory executable from HP core"
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depends on ESP_SYSTEM_MEMPROT&& IDF_TARGET_ARCH_RISCV && SOC_LP_CORE_SUPPORTED && ESP_SYSTEM_MEMPROT_PMP
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default n
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help
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If enabled, user can run code available in LP Core image.
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Warning: on ESP32-P4 this will also mark the memory area used for BOOTLOADER_RESERVE_RTC_MEM
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as executable. If you consider this a security risk then do not activate this option.
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config ESP_SYSTEM_EVENT_QUEUE_SIZE
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int "System event queue size"
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default 32
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help
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Config system event queue size in different application.
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config ESP_SYSTEM_EVENT_TASK_STACK_SIZE
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int "Event loop task stack size"
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default 2304
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help
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Config system event task stack size in different application.
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config ESP_MAIN_TASK_STACK_SIZE
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int "Main task stack size"
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default 3584
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help
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Configure the "main task" stack size. This is the stack of the task
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which calls app_main(). If app_main() returns then this task is deleted
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and its stack memory is freed.
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choice ESP_MAIN_TASK_AFFINITY
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prompt "Main task core affinity"
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default ESP_MAIN_TASK_AFFINITY_CPU0
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help
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Configure the "main task" core affinity. This is the used core of the task
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which calls app_main(). If app_main() returns then this task is deleted.
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config ESP_MAIN_TASK_AFFINITY_CPU0
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bool "CPU0"
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config ESP_MAIN_TASK_AFFINITY_CPU1
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bool "CPU1"
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depends on !FREERTOS_UNICORE
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config ESP_MAIN_TASK_AFFINITY_NO_AFFINITY
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bool "No affinity"
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endchoice
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config ESP_MAIN_TASK_AFFINITY
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hex
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default 0x0 if ESP_MAIN_TASK_AFFINITY_CPU0
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default 0x1 if ESP_MAIN_TASK_AFFINITY_CPU1
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default FREERTOS_NO_AFFINITY if ESP_MAIN_TASK_AFFINITY_NO_AFFINITY
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config ESP_MINIMAL_SHARED_STACK_SIZE
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int "Minimal allowed size for shared stack"
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default 2048
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help
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Minimal value of size, in bytes, accepted to execute a expression
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with shared stack.
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config ESP_INT_WDT
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bool "Interrupt watchdog"
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depends on SOC_WDT_SUPPORTED
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default y
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help
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This watchdog timer can detect if the FreeRTOS tick interrupt has not been called for a certain time,
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either because a task turned off interrupts and did not turn them on for a long time, or because an
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interrupt handler did not return. It will try to invoke the panic handler first and failing that
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reset the SoC.
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config ESP_INT_WDT_TIMEOUT_MS
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int "Interrupt watchdog timeout (ms)"
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depends on ESP_INT_WDT
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default 300 if !SPIRAM
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default 800 if SPIRAM
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range 10 10000
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help
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The timeout of the watchdog, in milliseconds. Make this higher than the FreeRTOS tick rate.
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config ESP_INT_WDT_CHECK_CPU1
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bool "Also watch CPU1 tick interrupt"
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depends on ESP_INT_WDT && !FREERTOS_UNICORE
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default y
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help
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Also detect if interrupts on CPU 1 are disabled for too long.
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config ESP_TASK_WDT_EN
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bool "Enable Task Watchdog Timer"
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depends on SOC_WDT_SUPPORTED
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default y
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help
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The Task Watchdog Timer can be used to make sure individual tasks are still
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running. Enabling this option will enable the Task Watchdog Timer. It can be
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either initialized automatically at startup or initialized after startup
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(see Task Watchdog Timer API Reference)
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config ESP_TASK_WDT_USE_ESP_TIMER
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# Software implementation of Task Watchdog, handy for targets with only a single
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# Timer Group, such as the ESP32-C2
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bool
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depends on ESP_TASK_WDT_EN
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default y if IDF_TARGET_ESP32C2
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default n if !IDF_TARGET_ESP32C2
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select ESP_TIMER_SUPPORTS_ISR_DISPATCH_METHOD
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config ESP_TASK_WDT_INIT
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bool "Initialize Task Watchdog Timer on startup"
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depends on ESP_TASK_WDT_EN
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default y
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help
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Enabling this option will cause the Task Watchdog Timer to be initialized
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automatically at startup.
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config ESP_TASK_WDT_PANIC
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bool "Invoke panic handler on Task Watchdog timeout"
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depends on ESP_TASK_WDT_INIT
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default n
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help
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If this option is enabled, the Task Watchdog Timer will be configured to
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trigger the panic handler when it times out. This can also be configured
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at run time (see Task Watchdog Timer API Reference)
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config ESP_TASK_WDT_TIMEOUT_S
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int "Task Watchdog timeout period (seconds)"
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depends on ESP_TASK_WDT_INIT
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range 1 60
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default 5
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help
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Timeout period configuration for the Task Watchdog Timer in seconds.
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This is also configurable at run time (see Task Watchdog Timer API Reference)
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config ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0
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bool "Watch CPU0 Idle Task"
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depends on ESP_TASK_WDT_INIT
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default y
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help
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If this option is enabled, the Task Watchdog Timer will watch the CPU0
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Idle Task. Having the Task Watchdog watch the Idle Task allows for detection
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of CPU starvation as the Idle Task not being called is usually a symptom of
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CPU starvation. Starvation of the Idle Task is detrimental as FreeRTOS household
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tasks depend on the Idle Task getting some runtime every now and then.
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config ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1
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bool "Watch CPU1 Idle Task"
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depends on ESP_TASK_WDT_INIT && !FREERTOS_UNICORE
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default y
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help
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If this option is enabled, the Task Watchdog Timer will wach the CPU1
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Idle Task.
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config ESP_XT_WDT
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bool "Initialize XTAL32K watchdog timer on startup"
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depends on SOC_XT_WDT_SUPPORTED && (ESP_SYSTEM_RTC_EXT_OSC || ESP_SYSTEM_RTC_EXT_XTAL)
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default n
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help
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This watchdog timer can detect oscillation failure of the XTAL32K_CLK. When such a failure
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is detected the hardware can be set up to automatically switch to BACKUP32K_CLK and generate
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an interrupt.
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config ESP_XT_WDT_TIMEOUT
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int "XTAL32K watchdog timeout period"
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depends on ESP_XT_WDT
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range 1 255
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default 200
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help
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Timeout period configuration for the XTAL32K watchdog timer based on RTC_CLK.
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config ESP_XT_WDT_BACKUP_CLK_ENABLE
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bool "Automatically switch to BACKUP32K_CLK when timer expires"
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depends on ESP_XT_WDT
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default y
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help
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Enable this to automatically switch to BACKUP32K_CLK as the source of RTC_SLOW_CLK when
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the watchdog timer expires.
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config ESP_PANIC_HANDLER_IRAM
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bool "Place panic handler code in IRAM"
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default n
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help
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If this option is disabled (default), the panic handler code is placed in flash not IRAM.
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This means that if ESP-IDF crashes while flash cache is disabled, the panic handler will
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automatically re-enable flash cache before running GDB Stub or Core Dump. This adds some minor
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risk, if the flash cache status is also corrupted during the crash.
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If this option is enabled, the panic handler code (including required UART functions) is placed
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in IRAM. This may be necessary to debug some complex issues with crashes while flash cache is
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disabled (for example, when writing to SPI flash) or when flash cache is corrupted when an exception
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is triggered.
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config ESP_DEBUG_STUBS_ENABLE
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bool "OpenOCD debug stubs"
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default COMPILER_OPTIMIZATION_LEVEL_DEBUG
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depends on !ESP32_TRAX && !ESP32S2_TRAX && !ESP32S3_TRAX
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help
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Debug stubs are used by OpenOCD to execute pre-compiled onboard code
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which does some useful debugging stuff, e.g. GCOV data dump.
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config ESP_DEBUG_INCLUDE_OCD_STUB_BINS
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bool "Preload OpenOCD stub binaries to speed up debugging. 8K memory will be reserved"
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default n
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depends on SOC_DEBUG_HAVE_OCD_STUB_BINS
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help
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OpenOCD uses stub code to access flash during programming or when inserting and removing
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SW flash breakpoints.
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To execute stub code, OpenOCD allocates memory on the target device, backs up the existing memory,
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loads the stub binary, runs the binary, and then restores the original memory.
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This process can be time-consuming, especially when using USB serial JTAG.
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By enabling this option, 8K of memory in RAM will be preallocated with the stub code,
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eliminating the need to back up and restore the memory region.
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config ESP_DEBUG_OCDAWARE
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bool "Make exception and panic handlers JTAG/OCD aware"
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default y
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select FREERTOS_DEBUG_OCDAWARE
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help
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The FreeRTOS panic and unhandled exception handlers can detect a JTAG OCD debugger and
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instead of panicking, have the debugger stop on the offending instruction.
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choice ESP_SYSTEM_CHECK_INT_LEVEL
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prompt "Interrupt level to use for Interrupt Watchdog and other system checks"
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default ESP_SYSTEM_CHECK_INT_LEVEL_4
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help
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Interrupt level to use for Interrupt Watchdog, IPC_ISR and other system checks.
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config ESP_SYSTEM_CHECK_INT_LEVEL_5
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bool "Level 5 interrupt"
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depends on IDF_TARGET_ESP32
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help
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Using level 5 interrupt for Interrupt Watchdog, IPC_ISR and other system checks.
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config ESP_SYSTEM_CHECK_INT_LEVEL_4
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bool "Level 4 interrupt"
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depends on !BTDM_CTRL_HLI
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help
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Using level 4 interrupt for Interrupt Watchdog, IPC_ISR and other system checks.
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endchoice
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# Insert chip-specific system config
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orsource "./port/soc/$IDF_TARGET/Kconfig.system"
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config ESP_SYSTEM_HW_STACK_GUARD
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bool "Hardware stack guard"
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depends on SOC_ASSIST_DEBUG_SUPPORTED
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default y
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help
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This config allows to trigger a panic interrupt when Stack Pointer register goes out of allocated stack
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memory bounds.
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config ESP_SYSTEM_BBPLL_RECALIB
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bool "Re-calibration BBPLL at startup"
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depends on IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32C6 || IDF_TARGET_ESP32H2
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default y
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help
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This configuration helps to address an BBPLL inaccurate issue when boot from certain bootloader version,
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which may increase about the boot-up time by about 200 us. Disable this when your bootloader is built with
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ESP-IDF version v5.2 and above.
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config ESP_SYSTEM_HW_PC_RECORD
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bool "Hardware PC recording"
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depends on SOC_ASSIST_DEBUG_SUPPORTED
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default y
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help
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This option will enable the PC recording function of assist_debug module. The PC value of the CPU will be
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recorded to PC record register in assist_debug module in real time. When an exception occurs and the CPU
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is reset, this register will be kept, then we can use the recorded PC to debug the causes of the reset.
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endmenu # ESP System Settings
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menu "IPC (Inter-Processor Call)"
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config ESP_IPC_ENABLE
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bool
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default y if !ESP_SYSTEM_SINGLE_CORE_MODE
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config ESP_IPC_TASK_STACK_SIZE
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int "Inter-Processor Call (IPC) task stack size"
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range 512 65536 if !APPTRACE_ENABLE
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range 2048 65536 if APPTRACE_ENABLE
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default 2048 if APPTRACE_ENABLE
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default 1280 if !APPTRACE_ENABLE && IDF_TARGET_ESP32S3
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default 1024
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help
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Configure the IPC tasks stack size. An IPC task runs on each core (in dual core mode), and allows for
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cross-core function calls. See IPC documentation for more details. The default IPC stack size should be
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enough for most common simple use cases. However, users can increase/decrease the stack size to their
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needs.
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config ESP_IPC_USES_CALLERS_PRIORITY
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bool "IPC runs at caller's priority"
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default y
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depends on ESP_IPC_ENABLE
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help
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If this option is not enabled then the IPC task will keep behavior same as prior to that of ESP-IDF v4.0,
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hence IPC task will run at (configMAX_PRIORITIES - 1) priority.
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config ESP_IPC_ISR_ENABLE
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bool
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default y if !ESP_SYSTEM_SINGLE_CORE_MODE
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help
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The IPC ISR feature is similar to the IPC feature except that the callback function is executed in the
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context of a High Priority Interrupt. The IPC ISR feature is intended for low latency execution of simple
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callbacks written in assembly on another CPU. Due to being run in a High Priority Interrupt, the assembly
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callbacks must be written with particular restrictions (see "IPC" and "High-Level Interrupt" docs for more
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details).
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endmenu # "IPC (Inter-Processor Call)
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